# 1 "apt32f102_interrupt.c"
# 1 "E:\\APT_Landscape_mode\\APT32F1023_New\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "apt32f102_interrupt.c"
# 19 "apt32f102_interrupt.c"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 20 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_adc.h" 1
# 23 "include/apt32f102_adc.h"
# 1 "include/apt32f102.h" 1
# 24 "include/apt32f102_adc.h" 2
# 46 "include/apt32f102_adc.h"
typedef enum
{
 ADC12_SWRST = ((CSP_REGISTER_T)(0x01ul << 0)),
 ADC12_ADCEN = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_ADCDIS = ((CSP_REGISTER_T)(0x01ul << 2)),
 ADC12_START = ((CSP_REGISTER_T)(0x01ul << 3)),
 ADC12_STOP = ((CSP_REGISTER_T)(0x01ul << 4)),
 ADC12_SWTRG = ((CSP_REGISTER_T)(0x01ul << 5)),
 ADC12_AVGEN = ((CSP_REGISTER_T)(0x01ul << 12)),
 ADC12_AVGDIS = ((CSP_REGISTER_T)(0x00ul << 12)),
}ADC12_Control_TypeDef;



typedef enum
{

 ADC12_EOC = ((CSP_REGISTER_T)(0x01ul << 0)),
 ADC12_READY = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_OVR = ((CSP_REGISTER_T)(0x01ul << 2)),
 ADC12_CMP0H = ((CSP_REGISTER_T)(0x01ul << 4)),
 ADC12_CMP0L = ((CSP_REGISTER_T)(0x01ul << 5)),
 ADC12_CMP1H = ((CSP_REGISTER_T)(0x01ul << 6)),
 ADC12_CMP1L = ((CSP_REGISTER_T)(0x01ul << 7)),
 ADC12_SEQ_END0 = ((CSP_REGISTER_T)(0x01ul << 16)),
 ADC12_SEQ_END1 = ((CSP_REGISTER_T)(0x01ul << 17)),
 ADC12_SEQ_END2 = ((CSP_REGISTER_T)(0x01ul << 18)),
 ADC12_SEQ_END3 = ((CSP_REGISTER_T)(0x01ul << 19)),
 ADC12_SEQ_END4 = ((CSP_REGISTER_T)(0x01ul << 20)),
 ADC12_SEQ_END5 = ((CSP_REGISTER_T)(0x01ul << 21)),
 ADC12_SEQ_END6 = ((CSP_REGISTER_T)(0x01ul << 22)),
 ADC12_SEQ_END7 = ((CSP_REGISTER_T)(0x01ul << 23)),
 ADC12_SEQ_END8 = ((CSP_REGISTER_T)(0x01ul << 24)),
 ADC12_SEQ_END9 = ((CSP_REGISTER_T)(0x01ul << 25)),
 ADC12_SEQ_END10 = ((CSP_REGISTER_T)(0x01ul << 26)),
 ADC12_SEQ_END11 = ((CSP_REGISTER_T)(0x01ul << 27)),
 ADC12_SEQ_END12 = ((CSP_REGISTER_T)(0x01ul << 28)),
 ADC12_SEQ_END13 = ((CSP_REGISTER_T)(0x01ul << 29)),
 ADC12_SEQ_END14 = ((CSP_REGISTER_T)(0x01ul << 30)),
 ADC12_SEQ_END15 = ((CSP_REGISTER_T)(0x01ul << 31)),

 ADC12_ADCENS = ((CSP_REGISTER_T)(0x01ul << 8)),
 ADC12_CTCVS = ((CSP_REGISTER_T)(0x01ul << 9))
}
ADC12_IMR_TypeDef;



typedef enum
{
 ADC_CLK_CR = ((CSP_REGISTER_T)(0x01ul << 1)),
 ADC12_IPIDCODE_MASK = ((CSP_REGISTER_T)(0x3FFFFFFul << 4)),
 ADC_DEBUG_MODE = ((CSP_REGISTER_T)(0x01ul << 31))
}
ADC12_CLK_TypeDef;



typedef enum
{
 ADC12_12BIT = 1,
 ADC12_10BIT = 0,
 ADC12_10BITor12BIT = ((CSP_REGISTER_T)(0x01ul<<31))
}ADC12_10bitor12bit_TypeDef;



typedef enum
{
 One_shot_mode = 0,
 Continuous_mode = 1,
 CONTCV = (CSP_REGISTER_T)0x01<<31
}ADC12_ConverMode_TypeDef;



typedef enum
{
 NBRCMP0_TypeDef = 0,
 NBRCMP1_TypeDef = 1
}
ADC12_NBRCMPx_TypeDef;



typedef enum
{
 NBRCMPX_L_TypeDef = 0,
 NBRCMPX_H_TypeDef = 1
}
ADC12_NBRCMPx_HorL_TypeDef;



typedef enum
{
  ADC12_ADCIN0 = (CSP_REGISTER_T)(0x0ul),
  ADC12_ADCIN1 = (CSP_REGISTER_T)(0x1ul),
  ADC12_ADCIN2 = (CSP_REGISTER_T)(0x2ul),
  ADC12_ADCIN3 = (CSP_REGISTER_T)(0x3ul),
  ADC12_ADCIN4 = (CSP_REGISTER_T)(0x4ul),
  ADC12_ADCIN5 = (CSP_REGISTER_T)(0x5ul),
  ADC12_ADCIN6 = (CSP_REGISTER_T)(0x6ul),
  ADC12_ADCIN7 = (CSP_REGISTER_T)(0x7ul),
  ADC12_ADCIN8 = (CSP_REGISTER_T)(0x8ul),
  ADC12_ADCIN9 = (CSP_REGISTER_T)(0x9ul),
  ADC12_ADCIN10 = (CSP_REGISTER_T)(0x0Aul),
  ADC12_ADCIN11 = (CSP_REGISTER_T)(0x0Bul),
  ADC12_ADCIN12 = (CSP_REGISTER_T)(0x0Cul),
  ADC12_ADCIN13 = (CSP_REGISTER_T)(0x0Dul),
  ADC12_ADCIN14 = (CSP_REGISTER_T)(0x0Eul),
  ADC12_ADCIN15 = (CSP_REGISTER_T)(0x0Ful),
# 170 "include/apt32f102_adc.h"
  ADC12_INTVREF = (CSP_REGISTER_T)(0x1Cul),
  ADC12_DIV4_VDD = (CSP_REGISTER_T)(0x1Dul),
  ADC12_VSS = (CSP_REGISTER_T)(0x1Eul),
}
ADC12_InputSet_TypeDef;




typedef enum
{
  ADC12_CV_RepeatNum1 = (CSP_REGISTER_T)(0x0ul<<8)|(0x0ul<<13),
  ADC12_CV_RepeatNum2 = (CSP_REGISTER_T)(0x1ul<<8)|(0x1ul<<13),
  ADC12_CV_RepeatNum4 = (CSP_REGISTER_T)(0x2ul<<8)|(0x2ul<<13),
  ADC12_CV_RepeatNum8 = (CSP_REGISTER_T)(0x3ul<<8)|(0x3ul<<13),
  ADC12_CV_RepeatNum16 = (CSP_REGISTER_T)(0x4ul<<8)|(0x4ul<<13),
  ADC12_CV_RepeatNum32 = (CSP_REGISTER_T)(0x5ul<<8)|(0x5ul<<13),
  ADC12_CV_RepeatNum64 = (CSP_REGISTER_T)(0x6ul<<8)|(0x6ul<<13),
  ADC12_CV_RepeatNum128 = (CSP_REGISTER_T)(0x7ul<<8)|(0x7ul<<13),
  ADC12_CV_RepeatNum256 = (CSP_REGISTER_T)(0x8ul<<8)|(0x8ul<<13),
  ADC12_CV_RepeatNum512 = (CSP_REGISTER_T)(0x9ul<<8)|(0x9ul<<13)
}ADC12_CV_RepeatNum_TypeDef;




typedef enum
{
 ADC12_VREFP_VDD_VREFN_VSS = 0,
 ADC12_VREFP_EXIT_VREFN_VSS = 1,
 ADC12_VREFP_FVR2048_VREFN_VSS = 2,
 ADC12_VREFP_FVR4096_VREFN_VSS = 3,

 ADC12_VREFP_INTVREF1000_VREFN_VSS = 5,
 ADC12_VREFP_VDD_VREFN_EXIT = 6,
 ADC12_VREFP_EXIT_VREFN_EXIT = 7,
 ADC12_VREFP_FVR2048_VREFN_EXIT = 8,
 ADC12_VREFP_FVR4096_VREFN_EXIT = 9,

 ADC12_VREFP_INTVREF1000_VREFN_EXIT = 11
}ADC12_VREFP_VREFN_Selected_TypeDef;

extern void ADC12_RESET_VALUE(void);
extern void ADC12_Control(ADC12_Control_TypeDef ADC12_Control_x );
extern void ADC12_ConfigInterrupt_CMD( ADC12_IMR_TypeDef ADC_IMR_X , FunctionalStatus NewState);
extern unsigned char ADC12_Read_IntEnStatus(ADC12_IMR_TypeDef EnStatus_bit);
extern void ADC12_CLK_CMD(ADC12_CLK_TypeDef ADC_CLK_CMD , FunctionalStatus NewState);
extern void ADC12_Software_Reset(void);
extern void ADC12_CMD(FunctionalStatus NewState);
extern void ADC12_ready_wait(void);
extern void ADC12_EOC_wait(void);
extern void ADC12_SEQEND_wait(U8_T val);
extern U16_T ADC12_DATA_OUPUT(U16_T Data_index );
extern void ADC12_Configure_Mode(ADC12_10bitor12bit_TypeDef ADC12_BIT_SELECTED , ADC12_ConverMode_TypeDef ADC12_ConverMode , U8_T ADC12_PRI, U8_T adc12_SHR , U8_T ADC12_DIV , U8_T NumConver );
extern void ADC12_Configure_VREF_Selecte(ADC12_VREFP_VREFN_Selected_TypeDef ADC12_VREFP_X_VREFN_X );
extern void ADC12_CompareFunction_set(U8_T ConverNum_CM0 , U8_T ConverNum_CM1 , U16_T CMP0_data , U16_T CMP1_data );
extern void ADC12_ConversionChannel_Config(ADC12_InputSet_TypeDef ADC12_ADCINX ,
      ADC12_CV_RepeatNum_TypeDef CV_RepeatTime, ADC12_Control_TypeDef AVG_Set, U8_T SEQx);
extern U8_T ADC12_Compare_statue(ADC12_NBRCMPx_TypeDef ADC12_NBRCMPx, ADC12_NBRCMPx_HorL_TypeDef ADC12_NBRCMPx_HorL);
extern void ADC_Int_Enable(void);
extern void ADC_Int_Disable(void);
extern void ADC12_CONFIG(void);
extern void adc12_SHR_SET(U8_T adc12_SHR);
# 21 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_bt.h" 1
# 31 "include/apt32f102_bt.h"
typedef enum
{
  BT0_PA00 = 0,
  BT0_PA02 = 1,
  BT0_PA05 = 2,
  BT0_PB02 = 3,
  BT0_PB05 = 4,
  BT0_PA11 = 5,
  BT0_PA13 = 6,
  BT0_PA15 = 7,
  BT1_PA01 = 8,
  BT1_PA06 = 9,
  BT1_PA08 = 10,
  BT1_PA12 = 11,
  BT1_PA14 = 12,
  BT1_PB00 = 13,
  BT1_PB04 = 14,
}BT_Pin_TypeDef;



typedef enum
{
    BTCLK_DIS = 0,
 BTCLK_EN = 1,
}BT_CLK_TypeDef;



typedef enum
{
    BT_SHADOW = (0<<3),
 BT_IMMEDIATE= (1<<3),
}BT_SHDWSTP_TypeDef;



typedef enum
{
    BT_CONTINUOUS= (0<<4),
 BT_ONCE= (1<<4),
}BT_OPM_TypeDef;



typedef enum
{
    BT_PCLKDIV= (0<<5),
 BT_EXTCKM= (1<<5),
}BT_EXTCKM_TypeDef;



typedef enum
{
    BT_IDLE_LOW= (0<<6),
 BT_IDLE_HIGH= (1<<6),
}BT_IDLEST_TypeDef;



typedef enum
{
    BT_START_LOW= (0<<7),
 BT_START_HIGH= (1<<7),
}BT_STARTST_TypeDef;



typedef enum
{
    BT_SYNC_DIS= (0<<8),
 BT_SYNC_EN= (1<<8),
}BT_SYNCEN_TypeDef;



typedef enum
{
    BT_OSTMDX_CONTINUOUS= (0<<10),
 BT_OSTMDX_ONCE= (1<<10),
}BT_OSTMDX_TypeDef;



typedef enum
{
    BT_AREARM_DIS= (0<<14),
 BT_AREARM_EN= (1<<14),
}BT_AREARM_TypeDef;



typedef enum
{
    BT_SYNCMD_DIS= (0<<15),
 BT_SYNCMD_EN= (1<<15),
}BT_SYNCMD_TypeDef;



typedef enum
{
    BT_CNTRLD_EN= (0<<16),
 BT_CNTRLD_DIS= (1<<16),
}BT_CNTRLD_TypeDef;



typedef enum
{
    BT_TRGSRC_DIS= (0<<0),
 BT_TRGSRC_PEND= (1<<0),
 BT_TRGSRC_CMP= (2<<0),
 BT_TRGSRC_OVF= (3<<0),
}BT_TRGSRC_TypeDef;



typedef enum
{
    BT_TRGOE_DIS= (0<<20),
 BT_TRGOE_EN= (1<<20),
}BT_TRGOE_TypeDef;



typedef enum
{
 BT_PEND = (0x01 << 0),
 BT_CMP = (0x01 << 1),
 BT_OVF = (0x01 << 2),
 BT_EVTRG = (0x01 << 3),
}BT_IMSCR_TypeDef;


extern void BT_DeInit(CSP_BT_T *BTx);
extern void BT_IO_Init(BT_Pin_TypeDef BT_IONAME);
extern void BT_Start(CSP_BT_T *BTx);
extern void BT_Stop(CSP_BT_T *BTx);
extern void BT_Soft_Reset(CSP_BT_T *BTx);
extern void BT_Configure(CSP_BT_T *BTx,BT_CLK_TypeDef BTCLK,U16_T PSCR_DATA,BT_SHDWSTP_TypeDef BTSHDWSTP,BT_OPM_TypeDef BTOPM,BT_EXTCKM_TypeDef BTEXTCKM);
extern void BT_ControlSet_Configure(CSP_BT_T *BTx,BT_STARTST_TypeDef BTSTART,BT_IDLEST_TypeDef BTIDLE,BT_SYNCEN_TypeDef BTSYNC,BT_SYNCMD_TypeDef BTSYNCMD,
       BT_OSTMDX_TypeDef BTOSTMD,BT_AREARM_TypeDef BTAREARM,BT_CNTRLD_TypeDef BTCNTRLD);
extern void BT_Period_CMP_Write(CSP_BT_T *BTx,U16_T BTPRDR_DATA,U16_T BTCMP_DATA);
extern void BT_CNT_Write(CSP_BT_T *BTx,U16_T BTCNT_DATA);
extern U16_T BT_PRDR_Read(CSP_BT_T *BTx);
extern U16_T BT_CMP_Read(CSP_BT_T *BTx);
extern U16_T BT_CNT_Read(CSP_BT_T *BTx);
extern void BT_Trigger_Configure(CSP_BT_T *BTx,BT_TRGSRC_TypeDef BTTRG,BT_TRGOE_TypeDef BTTRGOE);
extern void BT_Soft_Tigger(CSP_BT_T *BTx);
extern void BT_ConfigInterrupt_CMD(CSP_BT_T *BTx,FunctionalStatus NewState,BT_IMSCR_TypeDef BT_IMSCR_X);
extern void BT0_INT_ENABLE(void);
extern void BT0_INT_DISABLE(void);
extern void BT1_INT_ENABLE(void);
extern void BT1_INT_DISABLE(void);
# 22 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_coret.h" 1
# 36 "include/apt32f102_coret.h"
extern void CORET_DeInit(void);
extern void CORET_Int_Enable(void);
extern void CORET_Int_Disable(void);
extern void CORET_WakeUp_Enable(void);
extern void CORET_WakeUp_Disable(void);
extern void CORET_start(void);
extern void CORET_stop(void);
extern void CORET_CLKSOURCE_EX(void);
extern void CORET_CLKSOURCE_IN(void);
extern void CORET_TICKINT_Enable(void);
extern void CORET_TICKINT_Disable(void);
extern void CORET_reload(void);
# 23 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_countera.h" 1
# 33 "include/apt32f102_countera.h"
typedef enum
{
    Period_NA = 0,
    Period_H = 1,
    Period_L = 2,
    Period_H_L = 3,
}CA_INT_TypeDef;



typedef enum
{
    DIV1 = ((0 & 0x03ul)<<4) ,
    DIV2 = ((1 & 0x03ul)<<4) ,
    DIV4 = ((2 & 0x03ul)<<4) ,
    DIV8 = ((3 & 0x03ul)<<4) ,
}CA_CLKDIV_TypeDef;



typedef enum
{
    ONESHOT_MODE = (0x00ul << 1),
    REPEAT_MODE = (0x01ul << 1),
}CA_Mode_TypeDef;



typedef enum
{
    CARRIER_OFF = (0x00ul << 25),
    CARRIER_ON = (0x01ul << 25),
}CA_CARRIER_TypeDef;



typedef enum
{
    OSP_LOW = 0,
    OSP_HIGH = 1,
}CA_OSP_TypeDef;



typedef enum
{
    HW_STROBE_0 = (0x01ul<<17),
    HW_STROBE_1 = (0x01ul<<18),
    SW_STROBE = (0x01ul<<16),
}CA_STROBE_TypeDef;



typedef enum
{
    ENVELOPE_0 = (0x00ul << 24),
    ENVELOPE_1 = (0x01ul << 24),
}CA_ENVELOPE_TypeDef;



typedef enum
{
    PENDREM_OFF = ((0 & 0x03ul)<<21),
    PENDREM_1 = ((1 & 0x03ul)<<21),
    PENDREM_2 = ((2 & 0x03ul)<<21),
}CA_PENDREM_TypeDef;



typedef enum
{
    MATCHREM_OFF = ((0 & 0x03ul)<<19),
    MATCHREM_1 = ((1 & 0x03ul)<<19),
    MATCHREM_2 = ((2 & 0x03ul)<<19),
}CA_MATCHREM_TypeDef;



typedef enum
{
   REMSTAT_0 = ((0 & 0x01ul)<<23),
   REMSTAT_1 = ((1 & 0x01ul)<<23),
}CA_REMSTAT_TypeDef;



typedef enum
{
   COUNTA_PB01 = 0,
   COUNTA_PA05 = 1,
   COUNTA_PA11 = 2,
}CA_COUNTAIO_TypeDef;



extern void COUNTA_Init(unsigned int Data_H,unsigned int Data_L,CA_INT_TypeDef INT_Mode,
                     CA_CLKDIV_TypeDef DIVx,CA_Mode_TypeDef Mode,CA_CARRIER_TypeDef Carrier,
                     CA_OSP_TypeDef OSP_Mode) ;
extern void COUNTA_Config(CA_STROBE_TypeDef STROBE,CA_PENDREM_TypeDef Pend_CON,
                        CA_MATCHREM_TypeDef Match_CON,CA_REMSTAT_TypeDef Stat_CON,CA_ENVELOPE_TypeDef ENVELOPE );
extern void COUNT_DeInit(void);
extern void COUNTA_Start(void);
extern void COUNTA_Stop(void);
extern void COUNTA_Int_Disable(void);
extern void COUNTA_Int_Enable(void);
extern void COUNTA_Wakeup_Disable(void);
extern void COUNTA_Wakeup_Enable(void);
extern void COUNTA_IO_Init(CA_COUNTAIO_TypeDef COUNTA_IO_G);
extern void COUNTA_Data_Update(unsigned int Data_H,unsigned int Data_L);
# 24 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_crc.h" 1
# 32 "include/apt32f102_crc.h"
typedef enum
{
    XORIN_DIS = 0,
 XORIN_EN = 1,
}CRC_COMPIN_TypeDef;



typedef enum
{
    XOROUT_DIS = (0<<1),
 XOROUT_EN = (1<<1),
}CRC_COMPOUT_TypeDef;



typedef enum
{
    REFIN_DIS = (0<<2),
 REFIN_EN = (1<<2),
}CRC_ENDIANIN_TypeDef;



typedef enum
{
    REFOUT_DIS = (0<<3),
 REFOUT_EN = (1<<3),
}CRC_ENDIANOUT_TypeDef;



typedef enum
{
    POLY_CCITT = (0<<4),
 POLY_16 = (2<<4),
 POLY_32 = (3<<4),
}CRC_POLY_TypeDef;


extern void CRC_CMD(FunctionalStatus NewState);
extern void CRC_Soft_Reset(void);
extern void CRC_Configure(CRC_COMPIN_TypeDef COMPINX,CRC_COMPOUT_TypeDef COMPOUTX,CRC_ENDIANIN_TypeDef ENDIANINX,
       CRC_ENDIANOUT_TypeDef ENDIANOUT,CRC_POLY_TypeDef POLYX);
extern void CRC_Seed_Write(U32_T seed_data);
extern U32_T CRC_Seed_Read(void);
extern void CRC_Datain(U32_T data_in);
extern U32_T CRC_Result_Read(void);
extern U32_T Chip_CRC_CRC32(U32_T *data, U32_T words);
extern U32_T Chip_CRC_CRC16(U16_T *data, U32_T size);
extern U32_T Chip_CRC_CRC8(U8_T *data, U32_T size);
# 25 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_ept.h" 1
# 30 "include/apt32f102_ept.h"
typedef enum
{
 EPT_IO_CHAX = 0,
 EPT_IO_CHAY = 1,
 EPT_IO_CHBX = 2,
 EPT_IO_CHBY = 3,
 EPT_IO_CHCX = 4,
 EPT_IO_CHCY = 5,
 EPT_IO_CHD = 6,
 EPT_IO_EPI = 7
}EPT_IO_Mode_Type;



typedef enum
{
 IO_NUM_PA07 = 0X10,
 IO_NUM_PA10 = 0X11,
 IO_NUM_PA15 = 0X12,
 IO_NUM_PB03 = 0X13,
 IO_NUM_PB05 = 0X14,
 IO_NUM_PA12 = 0X15,
 IO_NUM_PB02 = 0X16,
 IO_NUM_PA11 = 0X17,
 IO_NUM_PA14 = 0X18,
 IO_NUM_PB04 = 0X19,
 IO_NUM_PA05 = 0X1A,
 IO_NUM_PA08 = 0X1B,
 IO_NUM_PA03 = 0X1C,
 IO_NUM_PB00 = 0X1D,
 IO_NUM_PA04 = 0X1E,
 IO_NUM_PA09 = 0X1F,
 IO_NUM_PA013 = 0X20
}EPT_IO_NUM_Type;



typedef enum
{
 EPT_Selecte_PCLK = 0<<3,
 EPT_Selecte_SYNCUSR3 = 1<<3
}EPT_TCLK_Selecte_Type;



typedef enum
{
 EPT_CGSRC_TIN_BT0OUT = 0,
 EPT_CGSRC_TIN_BT1OUT = 1,
 EPT_CGSRC_CHAX = 2,
 EPT_CGSRC_CHBX = 3,
 EPT_CGSRC_DIS = 4
}EPT_CGSRC_TIN_Selecte_Type;

typedef enum
{
 EPT_BURST_ENABLE = 1<<9,
 EPT_BURST_DIABLE = 0<<9
}EPT_BURST_CMD_Type;



typedef enum
{
 EPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
 EPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}EPT_CNTMD_SELECTE_Type;



typedef enum
{
 EPT_OPM_Once = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_OPM_Continue = ((CSP_REGISTER_T)(0x00ul << 6))
}EPT_OPM_SELECTE_Type;



typedef enum
{
 EPT_CAP_EN = ((CSP_REGISTER_T)(0x01ul << 8)),
 EPT_CAP_DIS = ((CSP_REGISTER_T)(0x00ul << 8))
}EPT_CAPLDEN_CMD_Type;




typedef enum
{
 EPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
 EPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}EPT_CAPMD_SELECTE_Type;




typedef enum
{
 EPT_LDARST_EN = ((CSP_REGISTER_T)(0x00ul << 23)),
 EPT_LDARST_DIS = ((CSP_REGISTER_T)(0x01ul << 23))
}EPT_LOAD_CMPA_RST_CMD_Type;



typedef enum
{
 EPT_LDBRST_EN = ((CSP_REGISTER_T)(0x00ul << 24)),
 EPT_LDBRST_DIS = ((CSP_REGISTER_T)(0x01ul << 24))
}EPT_LOAD_CMPB_RST_CMD_Type;



typedef enum
{
 EPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
 EPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}EPT_LOAD_CMPC_RST_CMD_Type;



typedef enum
{
 EPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
 EPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}EPT_LOAD_CMPD_RST_CMD_Type;



typedef enum
{
 EPT_FLT_DIS = ((CSP_REGISTER_T)(0x00ul << 10)),
 EPT_FLT_EN = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_FLT_CMD_Type;



typedef enum
{
 EPT_FLT_Bypass = ((CSP_REGISTER_T)(0x00ul << 13)),
 EPT_FLT_2 = ((CSP_REGISTER_T)(0x01ul << 13)),
 EPT_FLT_3 = ((CSP_REGISTER_T)(0x02ul << 13)),
 EPT_FLT_4 = ((CSP_REGISTER_T)(0x03ul << 13)),
 EPT_FLT_6 = ((CSP_REGISTER_T)(0x04ul << 13)),
 EPT_FLT_8 = ((CSP_REGISTER_T)(0x05ul << 13)),
 EPT_FLT_16 = ((CSP_REGISTER_T)(0x06ul << 13)),
 EPT_FLT_32 = ((CSP_REGISTER_T)(0x07ul << 13))
}EPT_FLT_CGFLT_Type;



typedef enum
{
 EPT_Triggle_Continue = ((CSP_REGISTER_T)(0x00ul << 8)),
 EPT_Triggle_Once = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_Triggle_Mode_Type;



typedef enum
{
 EPT_REARM_SYNCEN0 = ((CSP_REGISTER_T)(0x01ul << 16)),
 EPT_REARM_SYNCEN1 = ((CSP_REGISTER_T)(0x02ul << 16)),
 EPT_REARM_SYNCEN2 = ((CSP_REGISTER_T)(0x04ul << 16)),
 EPT_REARM_SYNCEN3 = ((CSP_REGISTER_T)(0x08ul << 16)),
 EPT_REARM_SYNCEN4 = ((CSP_REGISTER_T)(0x10ul << 16)),
 EPT_REARM_SYNCEN5 = ((CSP_REGISTER_T)(0x20ul << 16))
}EPT_REARMX_Type;



typedef enum
{
 EPT_REARM_Selected_DIS = ((CSP_REGISTER_T)(0x00ul << 30)),
 EPT_REARM_Selected_ZRO_AUTO = ((CSP_REGISTER_T)(0x01ul << 30)),
 EPT_REARM_Selected_PRD_AUTO = ((CSP_REGISTER_T)(0x02ul << 30)),
 EPT_REARM_Selected_ZRO_PRD_AUTO = ((CSP_REGISTER_T)(0x03ul << 30))
}EPT_REARM_MODE_Type;



typedef enum
{
 EPT_SYNCUSR0_REARMTrig_DIS = ((CSP_REGISTER_T)(0x00ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T1 = ((CSP_REGISTER_T)(0x01ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T2 = ((CSP_REGISTER_T)(0x02ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T1T2 = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_SYNCUSR0_REARMTrig_Selecte_Type;



typedef enum
{
 EPT_TRGSRC0_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 24))
}EPT_TRGSRC0_ExtSync_Selected_Type;



typedef enum
{
 EPT_TRGSRC1_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 27))
}EPT_TRGSRC1_ExtSync_Selected_Type;



typedef enum
{
 EPT_PHSEN_DIS = ((CSP_REGISTER_T)(0x00ul << 8)),
 EPT_PHSEN_EN = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_PHSEN_CMD_Type;



typedef enum
{
 EPT_PHSDIR_increase = ((CSP_REGISTER_T)(0x01ul << 31)),
 EPT_PHSEN_decrease = ((CSP_REGISTER_T)(0x00ul << 31))
}EPT_PHSDIR_Type;



typedef enum
{
 EPT_GLDMD_Selecte_ZRO = ((CSP_REGISTER_T)(0x00ul << 1)),
 EPT_GLDMD_Selecte_PRD = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_GLDMD_Selecte_ZRO_PRD = ((CSP_REGISTER_T)(0x02ul << 1)),
 EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x03ul << 1)),
 EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x04ul << 1)),
 EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x05ul << 1)),
 EPT_GLDMD_Selecte_SW = ((CSP_REGISTER_T)(0x0Ful << 1))
}EPT_GLDMD_Selecte_Type;



typedef enum
{
 EPT_GLD_OneShot_DIS = ((CSP_REGISTER_T)(0x00ul << 5)),
 EPT_GLD_OneShot_EN = ((CSP_REGISTER_T)(0x01ul << 5))
}EPT_GLD_OneShot_CMD_Type;



typedef enum
{
 EPT_PRDR_EventLoad_PEND = ((CSP_REGISTER_T)(0x00ul << 4)),
 EPT_PRDR_EventLoad_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x02ul << 4)),
 EPT_PRDR_EventLoad_Immediate = ((CSP_REGISTER_T)(0x03ul << 4))
} EPT_PRDR_EventLoad_Type;




typedef enum
{
 EPT_CMPX_EventLoad_DIS = 0,
 EPT_CMPX_EventLoad_Immediate = 1,
 EPT_CMPX_EventLoad_ZRO = 2,
 EPT_CMPX_EventLoad_PRD = 3,
 EPT_CMPX_EventLoad_ExiLoad_SYNC = 4
}EPT_CMPX_EventLoad_Type;



typedef enum
{
 EPT_AQCRX_EventLoad_DIS = 0,
 EPT_AQCRX_EventLoad_Immediate = 1,
 EPT_AQCRX_EventLoad_ZRO = 2,
 EPT_AQCRX_EventLoad_PRD = 3,
 EPT_AQCRX_EventLoad_ExiLoad_SYNC = 4
}EPT_AQCRX_EventLoad_Type;



typedef enum
{
 EPT_PWMA = 0,
 EPT_PWMB = 1,
 EPT_PWMC = 2,
 EPT_PWMD = 3
}EPT_PWMX_Selecte_Type;



typedef enum
{
 EPT_CA_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 20)),
 EPT_CA_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 20)),
 EPT_CA_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 20)),
 EPT_CA_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 20))
}EPT_CA_Selecte_Type;



typedef enum
{
 EPT_CB_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 22)),
 EPT_CB_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 22)),
 EPT_CB_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 22)),
 EPT_CB_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_CB_Selecte_Type;



typedef enum
{
 EPT_PWM_ZRO_Event_Nochange = ((CSP_REGISTER_T)(0x00ul )),
 EPT_PWM_ZRO_Event_OutLow = ((CSP_REGISTER_T)(0x01ul )),
 EPT_PWM_ZRO_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul )),
 EPT_PWM_ZRO_Event_Negate = ((CSP_REGISTER_T)(0x03ul ))
}EPT_PWM_ZRO_Output_Type;



typedef enum
{
 EPT_PWM_PRD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<2 )),
 EPT_PWM_PRD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<2 )),
 EPT_PWM_PRD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<2 )),
 EPT_PWM_PRD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<2 ))
}EPT_PWM_PRD_Output_Type;



typedef enum
{
 EPT_PWM_CAU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<4 )),
 EPT_PWM_CAU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<4 )),
 EPT_PWM_CAU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<4 )),
 EPT_PWM_CAU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<4 ))
}EPT_PWM_CAU_Output_Type;



typedef enum
{
 EPT_PWM_CAD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<6 )),
 EPT_PWM_CAD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<6 )),
 EPT_PWM_CAD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<6 )),
 EPT_PWM_CAD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<6 ))
}EPT_PWM_CAD_Output_Type;



typedef enum
{
 EPT_PWM_CBU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<8 )),
 EPT_PWM_CBU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<8 )),
 EPT_PWM_CBU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<8 )),
 EPT_PWM_CBU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<8 ))
}EPT_PWM_CBU_Output_Type;



typedef enum
{
 EPT_PWM_CBD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<10 )),
 EPT_PWM_CBD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<10 )),
 EPT_PWM_CBD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<10 )),
 EPT_PWM_CBD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<10 ))
}EPT_PWM_CBD_Output_Type;



typedef enum
{
 EPT_PWM_T1U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<12 )),
 EPT_PWM_T1U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<12 )),
 EPT_PWM_T1U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<12 )),
 EPT_PWM_T1U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<12 ))
}EPT_PWM_T1U_Output_Type;



typedef enum
{
 EPT_PWM_T1D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<14 )),
 EPT_PWM_T1D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<14 )),
 EPT_PWM_T1D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<14 )),
 EPT_PWM_T1D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<14 ))
}EPT_PWM_T1D_Output_Type;



typedef enum
{
 EPT_PWM_T2U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<16 )),
 EPT_PWM_T2U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<16 )),
 EPT_PWM_T2U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<16 )),
 EPT_PWM_T2U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<16 ))
}EPT_PWM_T2U_Output_Type;



typedef enum
{
 EPT_PWM_T2D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<18 )),
 EPT_PWM_T2D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<18 )),
 EPT_PWM_T2D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<18 )),
 EPT_PWM_T2D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<18 ))
}EPT_PWM_T2D_Output_Type;



typedef enum
{
 EPT_CPCR_ENALBE = ((CSP_REGISTER_T)(0x01ul<<16 )),
 EPT_CPCR_Disable = ((CSP_REGISTER_T)(0x00ul<<16 ))
}EPT_CPCR_CMD_Type;



typedef enum
{
 EPT_CPCR_Source_TCLK = ((CSP_REGISTER_T)(0)),
 EPT_CPCR_Source_TIN_BT0OUT = ((CSP_REGISTER_T)(1)),
 EPT_CPCR_Source_TIN_BT1OUT = ((CSP_REGISTER_T)(2))
}EPT_CPCR_Source_Selecte_Type;



typedef enum
{
 EPT_CDUTY_DIS = ((CSP_REGISTER_T)(0<<11)),
 EPT_CDUTY_7_8 = ((CSP_REGISTER_T)(1<<11)),
 EPT_CDUTY_6_8 = ((CSP_REGISTER_T)(2<<11)),
 EPT_CDUTY_5_8 = ((CSP_REGISTER_T)(3<<11)),
 EPT_CDUTY_4_8 = ((CSP_REGISTER_T)(4<<11)),
 EPT_CDUTY_3_8 = ((CSP_REGISTER_T)(5<<11)),
 EPT_CDUTY_2_8 = ((CSP_REGISTER_T)(6<<11)),
 EPT_CDUTY_1_8 = ((CSP_REGISTER_T)(7<<11))
}EPT_CDUTY_Type;



typedef enum
{
 EPT_EP0 = 0,
 EPT_EP1 = 1,
 EPT_EP2 = 2,
 EPT_EP3 = 3,
 EPT_EP4 = 4,
 EPT_EP5 = 5,
 EPT_EP6 = 6,
 EPT_EP7 = 7
}EPT_EPX_Type;



typedef enum
{
 EPT_Input_selecte_EPI0 = ((CSP_REGISTER_T)(1)),
 EPT_Input_selecte_EPI1 = ((CSP_REGISTER_T)(2)),
 EPT_Input_selecte_EPI2 = ((CSP_REGISTER_T)(3)),
 EPT_Input_selecte_EPI3 = ((CSP_REGISTER_T)(4)),
 EPT_Input_selecte_EPI4 = ((CSP_REGISTER_T)(5)),
 EPT_Input_selecte_ORL0 = ((CSP_REGISTER_T)(0XE)),
 EPT_Input_selecte_ORL1 = ((CSP_REGISTER_T)(0XF))
}EPT_Input_selecte_Type;



typedef enum
{
 EPT_FLT_PACE0_DIS = ((CSP_REGISTER_T)(0<<8)),
 EPT_FLT_PACE0_2CLK = ((CSP_REGISTER_T)(1<<8)),
 EPT_FLT_PACE0_3CLK = ((CSP_REGISTER_T)(2<<8)),
 EPT_FLT_PACE0_4CLK = ((CSP_REGISTER_T)(3<<8))
}EPT_FLT_PACE0_Type;



typedef enum
{
 EPT_FLT_PACE1_DIS = ((CSP_REGISTER_T)(0<<10)),
 EPT_FLT_PACE1_2CLK = ((CSP_REGISTER_T)(1<<10)),
 EPT_FLT_PACE1_3CLK = ((CSP_REGISTER_T)(2<<10)),
 EPT_FLT_PACE1_4CLK = ((CSP_REGISTER_T)(3<<10))
}EPT_FLT_PACE1_Type;



typedef enum
{
 EPT_DB_EventLoad_DIS = 0,
 EPT_DB_EventLoad_Immediate = 1,
 EPT_DB_EventLoad_ZRO = 2,
 EPT_DB_EventLoad_PRD = 3,
 EPT_DB_EventLoad_ZRO_PRD = 4
}EPT_DB_EventLoad_Type;



typedef enum
{
 EPT_CHA_Selecte = 0,
 EPT_CHB_Selecte = 1,
 EPT_CHC_Selecte = 2,
}EPT_CHX_Selecte_Type;



typedef enum
{
 EPT_CHAINSEL_PWMA_RISE_FALL = ((CSP_REGISTER_T)(0<<4)),
 EPT_CHAINSEL_PWMB_RISE_PWMA_FALL = ((CSP_REGISTER_T)(1<<4)),
 EPT_CHAINSEL_PWMA_RISE_PWMB_FALL = ((CSP_REGISTER_T)(2<<4)),
 EPT_CHAINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(3<<4)),
 EPT_CHBINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(0<<12)),
 EPT_CHBINSEL_PWMC_RISE_PWMB_FALL = ((CSP_REGISTER_T)(1<<12)),
 EPT_CHBINSEL_PWMB_RISE_PWMC_FALL = ((CSP_REGISTER_T)(2<<12)),
 EPT_CHBINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(3<<12)),
 EPT_CHCINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(0<<20)),
 EPT_CHCINSEL_PWMD_RISE_PWMC_FALL = ((CSP_REGISTER_T)(1<<20)),
 EPT_CHCINSEL_PWMC_RISE_PWMD_FALL = ((CSP_REGISTER_T)(2<<20)),
 EPT_CHCINSEL_PWMD_RISE_FALL = ((CSP_REGISTER_T)(3<<20))
}EPT_INSEL_Type;



typedef enum
{
 EPT_CHA_OUTSEL_PWMA_PWMB_Bypass = ((CSP_REGISTER_T)(0)),
 EPT_CHA_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1)),
 EPT_CHA_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2)),
 EPT_CHA_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3)),
 EPT_CHB_OUTSEL_PWMB_PWMC_Bypass = ((CSP_REGISTER_T)(0<<8)),
 EPT_CHB_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<8)),
 EPT_CHB_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<8)),
 EPT_CHB_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<8)),
 EPT_CHC_OUTSEL_PWMC_PWMD_Bypass = ((CSP_REGISTER_T)(0<<16)),
 EPT_CHC_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<16)),
 EPT_CHC_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<16)),
 EPT_CHC_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<16))
}EPT_OUTSEL_Type;



typedef enum
{
 EPT_PA_PB_OUT_Direct = ((CSP_REGISTER_T)(0)),
 EPT_PA_OUT_Reverse = ((CSP_REGISTER_T)(1)),
 EPT_PB_OUT_Reverse = ((CSP_REGISTER_T)(2)),
 EPT_PA_PB_OUT_Reverse = ((CSP_REGISTER_T)(3))
}EPT_OUT_POLARITY_Type;



typedef enum
{
 EPT_PAtoCHX_PBtoCHY = ((CSP_REGISTER_T)(0)),
 EPT_PBtoCHX_PBtoCHY = ((CSP_REGISTER_T)(1)),
 EPT_PAtoCHX_PAtoCHY = ((CSP_REGISTER_T)(2)),
 EPT_PBtoCHX_PAtoCHY = ((CSP_REGISTER_T)(3))
}EPT_OUT_SWAP_Type;



typedef enum
{
 EPT_TRGSRC0 = 0,
 EPT_TRGSRC1 = 1,
 EPT_TRGSRC2 = 2,
 EPT_TRGSRC3 = 3
}EPT_TRGSRCX_Select_Type;



 typedef enum
{
 EPT_EVTRG_TRGSRCX_DIS = ((CSP_REGISTER_T)(0x00ul )),
 EPT_EVTRG_TRGSRCX_ZRO = ((CSP_REGISTER_T)(0x01ul )),
 EPT_EVTRG_TRGSRCX_PRD = ((CSP_REGISTER_T)(0x02ul )),
 EPT_EVTRG_TRGSRCX_ZROorPRD = ((CSP_REGISTER_T)(0x03ul )),
 EPT_EVTRG_TRGSRCX_CMPAU = ((CSP_REGISTER_T)(0x04ul )),
 EPT_EVTRG_TRGSRCX_CMPAD = ((CSP_REGISTER_T)(0x05ul )),
 EPT_EVTRG_TRGSRCX_CMPBU = ((CSP_REGISTER_T)(0x06ul )),
 EPT_EVTRG_TRGSRCX_CMPBD = ((CSP_REGISTER_T)(0x07ul )),
 EPT_EVTRG_TRGSRCX_CMPCU = ((CSP_REGISTER_T)(0x08ul )),
 EPT_EVTRG_TRGSRCX_CMPCD = ((CSP_REGISTER_T)(0x09ul )),
 EPT_EVTRG_TRGSRCX_CMPDU = ((CSP_REGISTER_T)(0x0Aul )),
 EPT_EVTRG_TRGSRCX_CMPDD = ((CSP_REGISTER_T)(0x0Bul )),
 EPT_EVTRG_TRGSRC01_ExtSync = ((CSP_REGISTER_T)(0x0Cul )),
 EPT_EVTRG_TRGSRC23_PeriodEnd = ((CSP_REGISTER_T)(0x0Cul )),
 EPT_EVTRG_TRGSRCX_PE0 = ((CSP_REGISTER_T)(0x0Dul )),
 EPT_EVTRG_TRGSRCX_PE1 = ((CSP_REGISTER_T)(0x0Eul )),
 EPT_EVTRG_TRGSRCX_PE2 = ((CSP_REGISTER_T)(0x0Ful ))
}EPT_EVTRG_TRGSRCX_TypeDef;
 typedef enum
{
 EPT_TRGSRCX_EN = ((CSP_REGISTER_T)0x00ul),
 EPT_TRGSRCX_DIS = ((CSP_REGISTER_T)0x01ul)
}EPT_TRGSRCX_CMD_TypeDef;



typedef enum
{

 EPT_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_TRGEV2_INT = ((CSP_REGISTER_T)(0x01ul << 2)),
 EPT_TRGEV3_INT = ((CSP_REGISTER_T)(0x01ul << 3)),
 EPT_CAP_LD0 = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_CAP_LD1 = ((CSP_REGISTER_T)(0x01ul << 5)),
 EPT_CAP_LD2 = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_CAP_LD3 = ((CSP_REGISTER_T)(0x01ul << 7)),
 EPT_CAU = ((CSP_REGISTER_T)(0x01ul <<8)),
 EPT_CAD = ((CSP_REGISTER_T)(0x01ul <<9)),
 EPT_CBU = ((CSP_REGISTER_T)(0x01ul <<10)),
 EPT_CBD = ((CSP_REGISTER_T)(0x01ul <<11)),
 EPT_CCU = ((CSP_REGISTER_T)(0x01ul <<12)),
 EPT_CCD = ((CSP_REGISTER_T)(0x01ul <<13)),
 EPT_CDU = ((CSP_REGISTER_T)(0x01ul <<14)),
 EPT_CDD = ((CSP_REGISTER_T)(0x01ul <<15)),
 EPT_PEND = ((CSP_REGISTER_T)(0x01ul <<16))
}EPT_INT_TypeDef;



typedef enum
{

 EPT_EP0_EMINT = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_EP1_EMINT = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_EP2_EMINT = ((CSP_REGISTER_T)(0x01ul << 2)),
 EPT_EP3_EMINT = ((CSP_REGISTER_T)(0x01ul << 3)),
 EPT_EP4_EMINT = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_EP5_EMINT = ((CSP_REGISTER_T)(0x01ul << 5)),
 EPT_EP6_EMINT = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_EP7_EMINT = ((CSP_REGISTER_T)(0x01ul << 7)),
 EPT_CPU_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 8)),
 EPT_MEM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 9)),
 EPT_EOM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_EMINT_TypeDef;



typedef enum
{
 EPT_LKCR_TRG_EP0 = 0,
 EPT_LKCR_TRG_EP1 = 2,
 EPT_LKCR_TRG_EP2 = 4,
 EPT_LKCR_TRG_EP3 = 6,
 EPT_LKCR_TRG_EP4 = 8,
 EPT_LKCR_TRG_EP5 = 10,
 EPT_LKCR_TRG_EP6 = 12,
 EPT_LKCR_TRG_EP7 = 14,
 EPT_LKCR_TRG_CPU_FAULT = 15,
 EPT_LKCR_TRG_MEM_FAULT = 16,
 EPT_LKCR_TRG_EOM_FAULT = 17
}EPT_LKCR_TRG_Source_Type;



typedef enum
{
 EPT_LKCR_Mode_LOCK_DIS = ((CSP_REGISTER_T)0x00ul),
 EPT_LKCR_Mode_SLOCK_EN = ((CSP_REGISTER_T)0x01ul),
 EPT_LKCR_Mode_HLOCK_EN = ((CSP_REGISTER_T)0x02ul),
 EPT_LKCR_TRG_X_FAULT_HLOCK_EN = ((CSP_REGISTER_T)0x03ul),
 EPT_LKCR_TRG_X_FAULT_HLOCK_DIS = ((CSP_REGISTER_T)0x04ul),
}EPT_LKCR_Mode_Type;



typedef enum
{
 EPT_OUTPUT_Channel_CHAX = 0,
 EPT_OUTPUT_Channel_CHBX = 2,
 EPT_OUTPUT_Channel_CHCX = 4,
 EPT_OUTPUT_Channel_CHD = 6,
 EPT_OUTPUT_Channel_CHAY = 8,
 EPT_OUTPUT_Channel_CHBY = 10,
 EPT_OUTPUT_Channel_CHCY = 12
}EPT_OUTPUT_Channel_Type;



typedef enum
{
 EPT_SHLOCK_OUTPUT_HImpedance = 0,
 EPT_SHLOCK_OUTPUT_High = 1,
 EPT_SHLOCK_OUTPUT_Low = 2,
 EPT_SHLOCK_OUTPUT_Nochange = 3
}EPT_SHLOCK_OUTPUT_Statue_Type;




extern void EPT_Software_Prg(void);
extern void EPT_Start(void);
extern void EPT_Stop(void);
extern void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X);
extern void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X
     , U16_T EPT_PSCR);
extern void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD);
extern void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD
     , EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD
     , EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR);
extern void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected ,
       EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN);
extern void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR);
extern void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX );
extern void EPT_Caputure_Rearm(void);
extern void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN);
extern void EPT_Globle_SwLoad_CMD(void);
extern void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV);
extern void EPT_PWMX_Output_Control(
        EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X ,
        EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output ,
        EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output ,
        EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output ,
        EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output ,
        EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output
        );
extern void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte);
extern void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value);
extern void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x);
extern void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x);
extern void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X);
extern void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx);
extern void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL);
extern void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X);
extern void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X);
extern void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF);
extern void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD);
extern void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select);
extern void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_Vector_Int_Enable(void);
extern void EPT_Vector_Int_Disable(void);
extern void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X);
extern void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X);
# 26 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_et.h" 1
# 33 "include/apt32f102_et.h"
typedef enum
{
    ET_SWTRG_CH0 = 0,
 ET_SWTRG_CH1 = (1<<1),
 ET_SWTRG_CH2 = (1<<2),
 ET_SWTRG_CH3 = (1<<3),
 ET_SWTRG_CH4 = (1<<4),
 ET_SWTRG_CH5 = (1<<5),
 ET_SWTRG_CH6 = (1<<6),
 ET_SWTRG_CH7 = (1<<7),
}CRC_ETSWTRG_TypeDef;



typedef enum
{
    ET_SRC0 = 0,
 ET_SRC1 = 1,
 ET_SRC2 = 2,
}CRC_ESRCSEL_TypeDef;



typedef enum
{
    ET_DST0 = 0,
 ET_DST1 = 1,
 ET_DST2 = 2,
}CRC_DSTSEL_TypeDef;



typedef enum
{
    ET_CH3 = 0,
 ET_CH4 = 1,
 ET_CH5 = 2,
 ET_CH6 = 3,
 ET_CH7 = 4,
}CRC_ETCHX_TypeDef;



typedef enum
{
    TRG_HW = (0X00<<1),
 TRG_SW = (0X01<<1),
}CRC_TRIGMODE_TypeDef;
# 132 "include/apt32f102_et.h"
extern void ET_DeInit(void);
extern void ET_ENABLE(void);
extern void ET_DISABLE(void);
extern void ET_SWTRG_CMD(CRC_ETSWTRG_TypeDef ETSWTRG_X,FunctionalStatus NewState);
extern void ET_CH0_SRCSEL(CRC_ESRCSEL_TypeDef ESRCSEL_X,FunctionalStatus NewState,U8_T SRCSEL_X);
extern void ET_CH0_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CH1_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X);
extern void ET_CH1_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CH2_SRCSEL(CRC_DSTSEL_TypeDef DST_X,FunctionalStatus NewState,U8_T DSTSEL_X);
extern void ET_CH2_CONTROL(FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T DSTSEL_X);
extern void ET_CHx_CONTROL(CRC_ETCHX_TypeDef ETCHX,FunctionalStatus NewState,CRC_TRIGMODE_TypeDef TRIGMODEX,U8_T SRCSEL_X,U8_T DSTSEL_X);
# 27 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_gpio.h" 1
# 33 "include/apt32f102_gpio.h"
typedef enum
{
  PIN_0 = 0,
  PIN_1 = 4,
  PIN_2 = 8,
  PIN_3 = 12,
  PIN_4 = 16,
  PIN_5 = 20,
  PIN_6 = 24,
  PIN_7 = 28,
  PIN_8 = 0,
  PIN_9 = 4,
  PIN_10 = 8,
  PIN_11 = 12,
  PIN_12 = 16,
  PIN_13 = 20,
  PIN_14 = 24,
  PIN_15 = 28,
}GPIO_Pin_TypeDef;



typedef enum
{
    LowByte = 0,
    HighByte = 1,
}GPIO_byte_TypeDef;



typedef enum
{
    Intput = 1,
    Output = 0,
}GPIO_Dir_TypeDef;



typedef enum
{
    PUDR = 0,
    DSCR =1,
    OMCR =2,
    IECR =3,
}GPIO_Mode_TypeDef;



typedef enum
{
    PA0 = 0,
    PB0 = 2,
    GPIOA = 0,
    GPIOB = 2,
}GPIO_Group_TypeDef;



typedef enum
{
    EXI0 = 0,
    EXI1 = 1,
    EXI2 = 2,
    EXI3 = 3,
    EXI4 = 4,
    EXI5 = 5,
    EXI6 = 6,
    EXI7 = 7,
    EXI8 = 8,
    EXI9 = 9,
    EXI10 = 10,
    EXI11 = 11,
    EXI12 = 12,
    EXI13 = 13,
 EXI14 = 14,
 EXI15 = 15,
}GPIO_EXI_TypeDef;




typedef enum
{
 Selete_EXI_PIN0 = (CSP_REGISTER_T)(0),
 Selete_EXI_PIN1 = (CSP_REGISTER_T)(1),
 Selete_EXI_PIN2 = (CSP_REGISTER_T)(2),
 Selete_EXI_PIN3 = (CSP_REGISTER_T)(3),
 Selete_EXI_PIN4 = (CSP_REGISTER_T)(4),
 Selete_EXI_PIN5 = (CSP_REGISTER_T)(5),
 Selete_EXI_PIN6 = (CSP_REGISTER_T)(6),
 Selete_EXI_PIN7 = (CSP_REGISTER_T)(7),
 Selete_EXI_PIN8 = (CSP_REGISTER_T)(8),
 Selete_EXI_PIN9 = (CSP_REGISTER_T)(9),
 Selete_EXI_PIN10 = (CSP_REGISTER_T)(10),
 Selete_EXI_PIN11 = (CSP_REGISTER_T)(11),
 Selete_EXI_PIN12 = (CSP_REGISTER_T)(12),
 Selete_EXI_PIN13 = (CSP_REGISTER_T)(13),
 Selete_EXI_PIN14 = (CSP_REGISTER_T)(14),
 Selete_EXI_PIN15 = (CSP_REGISTER_T)(15),
 Selete_EXI_PIN16 = (CSP_REGISTER_T)(16),
 Selete_EXI_PIN17 = (CSP_REGISTER_T)(17),
 Selete_EXI_PIN18 = (CSP_REGISTER_T)(18),
 Selete_EXI_PIN19 = (CSP_REGISTER_T)(19)
}GPIO_EXIPIN_TypeDef;





typedef enum
{
 INPUT_MODE_SETECTED_CMOS = 0,
 INPUT_MODE_SETECTED_TTL1 = 1,
 INPUT_MODE_SETECTED_TTL2 = 2
}INPUT_MODE_SETECTED_TypeDef;
# 190 "include/apt32f102_gpio.h"
extern void GPIOA0_DeInit(GPIO_Pin_TypeDef GPIO_Pin);
extern void GPIO_DeInit(void);
extern void GPIO_TTL_COSM_Selecte(CSP_GPIO_T *GPIOx,unsigned char bit,INPUT_MODE_SETECTED_TypeDef INPUT_MODE_SETECTED_X);
extern void GPIO_Init2(CSP_GPIO_T *GPIOx,GPIO_byte_TypeDef byte,unsigned int val);
extern void GPIO_InPutOutPut_Disable(CSP_GPIO_T *GPIOx,unsigned char PinNum);
extern void GPIO_Init(CSP_GPIO_T *GPIOx,unsigned char PinNum,GPIO_Dir_TypeDef Dir);
extern void GPIO_Write_Low(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_Write_High(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_MODE_Init(CSP_GPIO_T *GPIOx,GPIO_Mode_TypeDef IO_MODE,unsigned int val);
extern unsigned char GPIO_Read_Status(CSP_GPIO_T *GPIOx,unsigned char bit);
extern unsigned char GPIO_Read_Output(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_Reverse(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_Set_Value(CSP_GPIO_T *GPIOx,unsigned char bitposi,unsigned char bitval);
extern void GPIOA0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIOB0_EXI_Init(GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_EXI_EN(CSP_GPIO_T *GPIOx,GPIO_EXI_TypeDef EXI_IO);
extern void GPIO_Debug_IO_12_13(void);
extern void GPIO_Debug_IO_01_02(void);
extern void GPIO_IntGroup_Set(GPIO_Group_TypeDef IO_MODE , unsigned char PinNum , GPIO_EXIPIN_TypeDef EXIPIN_x);
extern void GPIOA00_Set_ResetPin();
extern void GPIO_PullHigh_Init(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_PullLow_Init(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_PullHighLow_DIS(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_OpenDrain_EN(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_OpenDrain_DIS(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_DriveStrength_EN(CSP_GPIO_T *GPIOx,unsigned char bit);
extern void GPIO_DriveStrength_DIS(CSP_GPIO_T *GPIOx,unsigned char bit);
# 28 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_gpt.h" 1
# 33 "include/apt32f102_gpt.h"
typedef enum
{
    GPTCLK_DIS = 0,
 GPTCLK_EN = 1,
}GPT_CLK_TypeDef;



typedef enum
{
    GPT_PCLK = (0<<2),
 GPT_TRGUSR3 = (1<<2),
}GPT_CSS_TypeDef;



typedef enum
{
    GPT_SHADOW = (0<<6),
 GPT_IMMEDIATE= (1<<6),
}GPT_SHDWSTP_TypeDef;



typedef enum
{
    DIR_INCREASE = (0<<3),
 DIR_DECREASE= (1<<3),
}GPT_CNTDIR_TypeDef;



typedef enum
{
    GPT_INCREASE = (0<<0),
 GPT_DECREASE= (1<<0),
 GPT_IN_DECREASE= (2<<0),
}GPT_CNTMD_TypeDef;



typedef enum
{
    GPT_SWSYNDIS= (0<<2),
 GPT_SWSYNEN= (1<<2),
}GPT_SWSYN_TypeDef;



typedef enum
{
    GPT_IDLE_Z= (0<<3),
 GPT_IDLE_LOW= (1<<3),
}GPT_IDLEST_TypeDef;



typedef enum
{
 GPT_PRDLD_PEND= (0<<4),
 GPT_PRDLD_LOAD_SYNC= (1<<4),
 GPT_PRDLD_ZERO_LOAD_SYNC= (2<<4),
 GPT_PRDLD_IMMEDIATELY= (3<<4),
}GPT_PRDLD0_TypeDef;



typedef enum
{
    GPT_CAP_DIS= (0<<8),
 GPT_CAP_EN= (1<<8),
}GPT_CAPLDEN_TypeDef;



typedef enum
{
    GPT_BURST_DIS= (0<<9),
 GPT_BURST_EN= (1<<9),
}GPT_BURST_TypeDef;



typedef enum
{
    GPT_CG_CHAX= (0<<11),
 GPT_CG_CHBX= (1<<11),
}GPT_CGSRC_TypeDef;



typedef enum
{
    GPT_CGFLT_00= (0<<13),
 GPT_CGFLT_02= (1<<13),
 GPT_CGFLT_03= (2<<13),
 GPT_CGFLT_04= (3<<13),
 GPT_CGFLT_06= (4<<13),
 GPT_CGFLT_08= (5<<13),
 GPT_CGFLT_16= (6<<13),
 GPT_CGFLT_32= (7<<13),
}GPT_CGFLT_TypeDef;



typedef enum
{
 GPT_PRDLD_ZERO= (0<<16),
 GPT_PRDLD_PRD= (1<<16),
 GPT_PRDLD_ZERO_PRD= (2<<16),
 GPT_PRDLD_NONE= (3<<16),
}GPT_PSCLD_TypeDef;



typedef enum
{
 GPT_CAPMD_CONTINUOUS= (0<<20),
 GPT_CAPMD_ONCE= (1<<20),
}GPT_CAPMD_TypeDef;



typedef enum
{
 GPT_LDARST_EN= (0<<23),
 GPT_LDARST_DIS= (1<<23),
}GPT_LDARST_TypeDef;



typedef enum
{
 GPT_LDBRST_EN= (0<<23),
 GPT_LDBRST_DIS= (1<<23),
}GPT_LDBRST_TypeDef;



typedef enum
{
 GPT_OPM_CONTINUOUS= (0<<6),
 GPT_OPM_ONCE= (1<<6),
}GPT_OPM_TypeDef;



typedef enum
{
 GPT_CKS_PCLK= (0<<10),
 GPT_CKS_PCLKDIV2= (1<<10),
}GPT_CKS_TypeDef;



typedef enum
{
 GPT_CAPTURE_MODE= (0<<18),
 GPT_WAVE_MODE= (1<<18),
}GPT_WAVE_TypeDef;



typedef enum
{
 GPT_SYNCUSR0_EN= (1<<0),
 GPT_SYNCUSR1_EN= (1<<0),
 GPT_SYNCUSR2_EN= (1<<0),
 GPT_SYNCUSR3_EN= (1<<0),
 GPT_SYNCUSR4_EN= (1<<0),
 GPT_SYNCUSR5_EN= (1<<0)
}GPT_SYNCENX_TypeDef;




typedef enum
{
 GPT_OST_CONTINUOUS= (0<<8),
 GPT_OST_ONCE= (1<<8),
}GPT_OSTMDX_TypeDef;



typedef enum
{
 GPT_TXREARM_DIS= (0<<22),
 GPT_TXREARM_T1= (1<<22),
 GPT_TXREARM_T2= (2<<22),
 GPT_TXREARM_T1_T2= (3<<22),
}GPT_TXREARM0_TypeDef;




typedef enum
{
 GPT_TRGO0SEL_SR0= (0<<24),
 GPT_TRGO0SEL_SR1= (1<<24),
 GPT_TRGO0SEL_SR2= (2<<24),
 GPT_TRGO0SEL_SR3= (3<<24),
 GPT_TRGO0SEL_SR4= (4<<24),
 GPT_TRGO0SEL_SR5= (5<<24),
 GPT_TRGO0SEL_RSVD= (6<<24),
}GPT_TRGO0SEL_TypeDef;




typedef enum
{
 GPT_TRG10SEL_SR0= (0<<27),
 GPT_TRG10SEL_SR1= (1<<27),
 GPT_TRG10SEL_SR2= (2<<27),
 GPT_TRG10SEL_SR3= (3<<27),
 GPT_TRG10SEL_SR4= (4<<27),
 GPT_TRG10SEL_SR5= (5<<27),
 GPT_TRG10SEL_RSVD= (6<<27),
}GPT_TRGO1SEL_TypeDef;



typedef enum
{
 GPT_AREARM_DIS= (0<<30),
 GPT_AREARM_ZERO= (1<<30),
 GPT_AREARM_PRD= (2<<30),
 GPT_AREARM_ZERO_PRD= (3<<30),
}GPT_AREARM_TypeDef;



typedef enum
{
 GPT_TRGEV0 = (0x01 << 0),
 GPT_TRGEV1 = (0x01 << 1),
 GPT_TRGEV2 = (0x01 << 2),
 GPT_TRGEV3 = (0x01 << 3),
}GPT_IMSCR_TypeDef;



typedef enum
{
 GPT_CHA_PB01 = 0,
 GPT_CHA_PA09 = 1,
 GPT_CHA_PA010 = 2,
 GPT_CHB_PA010 = 3,
 GPT_CHB_PA011 = 4,
 GPT_CHB_PB00 = 5,
 GPT_CHB_PB01 = 6,
}GPT_IOSET_TypeDef;



typedef enum
{
 GPT_CMPA_SHADOW = (0x00 << 0),
 GPT_CMPA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWCMPA_TypeDef;



typedef enum
{
 GPT_CMPB_SHADOW = (0x00 << 1),
 GPT_CMPB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWCMPB_TypeDef;



typedef enum
{
 GPT_LoadA_ZERO = (0x01 << 4),
 GPT_LoadA_PRD = (0x02 << 4),
 GPT_LoadA_EXT_SYNC = (0x04 << 4),
 GPT_LoadA_NONE = (0x00 << 4),
}GPT_LDAMD_TypeDef;



typedef enum
{
 GPT_LoadB_ZERO = (0x01 << 4),
 GPT_LoadB_PRD = (0x02 << 4),
 GPT_LoadB_EXT_SYNC = (0x04 << 4),
 GPT_LoadB_NONE = (0x00 << 4),
}GPT_LDBMD_TypeDef;




typedef enum
{
 GPT_WAVEA_SHADOW = (0x00 << 0),
 GPT_WAVEA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWAQA_TypeDef;



typedef enum
{
 GPT_WAVEB_SHADOW = (0x00 << 1),
 GPT_WAVEB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWAQB_TypeDef;



typedef enum
{
 GPT_AQLDA_ZERO = (0x01 << 2),
 GPT_AQLDA_PRD = (0x02 << 2),
 GPT_AQLDA_EXT_SYNC = (0x04 << 2),
 GPT_AQLDA_NONE = (0x00 << 2),
}GPT_AQLDA_TypeDef;



typedef enum
{
 GPT_AQLDB_ZERO = (0x01 << 5),
 GPT_AQLDB_PRD = (0x02 << 5),
 GPT_AQLDB_EXT_SYNC = (0x04 << 5),
 GPT_AQLDB_NONE = (0x00 << 5),
}GPT_AQLDB_TypeDef;



typedef enum
{
 GPT_CASEL_CMPA = (0x00 << 20),
 GPT_CASEL_CMPB = (0x01 << 20),
}GPT_CASEL_TypeDef;



typedef enum
{
 GPT_CBSEL_CMPA = (0x00 << 22),
 GPT_CBSEL_CMPB = (0x01 << 22),
}GPT_CBSEL_TypeDef;



typedef enum
{
 GPT_CHA = 0,
 GPT_CHB = 1,
}GPT_GPTCHX_TypeDef;



typedef enum
{
 GPT_CHA_FORCE_DIS = 0,
 GPT_CHA_FORCE_EN = 1,
}GPT_CHAFORCE_TypeDef;



typedef enum
{
 GPT_CHB_FORCE_DIS = 0<<4,
 GPT_CHB_FORCE_EN = 1<<4,
}GPT_CHBFORCE_TypeDef;



typedef enum
{
 GPT_FORCELD_ZERO = (0<<16),
 GPT_FORCELD_PRD = (1<<16),
 GPT_FORCELD__ZERO_PRD = (3<<16),
}GPT_FORCELD_TypeDef;



typedef enum
{
 GPT_FORCECHA_LOW = (1<<0),
 GPT_FORCECHA_HIGH = (2<<0),
}GPT_FORCEA_TypeDef;



typedef enum
{
 GPT_FORCECHB_LOW = (1<<2),
 GPT_FORCECHB_HIGH = (2<<2),
}GPT_FORCEB_TypeDef;



typedef enum
{
    GPT_SRCSEL_DIS= (0<<0),
 GPT_SRCSEL_TRGUSR0EN= (1<<0),
 GPT_SRCSEL_TRGUSR1EN= (2<<0),
 GPT_SRCSEL_TRGUSR2EN= (3<<0),
 GPT_SRCSEL_TRGUSR3EN= (4<<0),
 GPT_SRCSEL_TRGUSR4EN= (5<<0),
 GPT_SRCSEL_TRGUSR5EN= (6<<0)
}GPT_SRCSEL_TypeDef;



typedef enum
{
    GPT_BLKINV_DIS= (0<<4),
 GPT_BLKINV_EN= (1<<4),
}GPT_BLKINV_TypeDef;



typedef enum
{
    GPT_ALIGNMD_PRD= (0<<5),
 GPT_ALIGNMD_ZRO= (1<<5),
 GPT_ALIGNMD_PRD_ZRO= (2<<5),
 GPT_ALIGNMD_T1= (3<<5),
}GPT_ALIGNMD_TypeDef;



typedef enum
{
    GPT_CROSSMD_DIS= (0<<7),
 GPT_CROSSMD_EN= (1<<7),
}GPT_CROSSMD_TypeDef;



typedef enum
{
    GPT_TRGSRC0_DIS= (0<<0),
 GPT_TRGSRC0_ZRO= (1<<0),
 GPT_TRGSRC0_PRD= (2<<0),
 GPT_TRGSRC0_ZRO_PRD= (3<<0),
 GPT_TRGSRC0_CMPA_INC= (4<<0),
 GPT_TRGSRC0_CMPA_DEC= (5<<0),
 GPT_TRGSRC0_CMPB_INC= (6<<0),
 GPT_TRGSRC0_CMPB_DEC= (7<<0),
 GPT_TRGSRC0_EXTSYNC= (0X0C<<0),
 GPT_TRGSRC0_PE0= (0X0D<<0),
 GPT_TRGSRC0_PE1= (0X0E<<0),
 GPT_TRGSRC0_PE2= (0X0F<<0),
}GPT_TRGSRC0_TypeDef;



typedef enum
{
    GPT_TRGSRC1_DIS= (0<<4),
 GPT_TRGSRC1_ZRO= (1<<4),
 GPT_TRGSRC1_PRD= (2<<4),
 GPT_TRGSRC1_ZRO_PRD= (3<<4),
 GPT_TRGSRC1_CMPA_INC= (4<<4),
 GPT_TRGSRC1_CMPA_DEC= (5<<4),
 GPT_TRGSRC1_CMPB_INC= (6<<4),
 GPT_TRGSRC1_CMPB_DEC= (7<<4),
 GPT_TRGSRC1_EXTSYNC= (0X0C<<4),
 GPT_TRGSRC1_PE0= (0X0D<<4),
 GPT_TRGSRC1_PE1= (0X0E<<4),
 GPT_TRGSRC1_PE2= (0X0F<<4),
}GPT_TRGSRC1_TypeDef;




typedef enum
{
    GPT_CNT0INIT_DIS= (0<<16),
 GPT_CNT0INIT_EN= (1<<16),
}GPT_CNT0INIT_TypeDef;




typedef enum
{
    GPT_CNT1INIT_DIS= (0<<17),
 GPT_CNT1INIT_EN= (1<<17),
}GPT_CNT1INIT_TypeDef;




typedef enum
{
    GPT_ESYN0OE_DIS= (0<<20),
 GPT_ESYN0OE_EN= (1<<20),
}GPT_ESYN0OE_TypeDef;




typedef enum
{
    GPT_ESYN1OE_DIS= (0<<21),
 GPT_ESYN1OE_EN= (1<<21),
}GPT_ESYN1OE_TypeDef;





typedef enum
{
 GPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
 GPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
 GPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}GPT_CNTMD_SELECTE_Type;




typedef enum
{
 GPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
 GPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}GPT_CAPMD_SELECTE_Type;




typedef enum
{
 GPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
 GPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}GPT_LOAD_CMPC_RST_CMD_Type;



typedef enum
{
 GPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
 GPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}GPT_LOAD_CMPD_RST_CMD_Type;
# 646 "include/apt32f102_gpt.h"
extern void GPT_DeInit(void);
extern void GPT_IO_Init(GPT_IOSET_TypeDef IONAME);
extern void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX);
extern void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
      GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX);
extern void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX);
extern void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
      U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX);
extern void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX);
extern void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX);
extern void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX);
extern void GPT_Debug_Mode(FunctionalStatus NewState);
extern void GPT_Start(void);
extern void GPT_Stop(void);
extern void GPT_Soft_Reset(void);
extern void GPT_Cap_Rearm(void);
extern void GPT_REARM_Write(void);
extern U8_T GPT_REARM_Read(void);
extern void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA);
extern U16_T GPT_PRDR_Read(void);
extern U16_T GPT_CMPA_Read(void);
extern U16_T GPT_CMPB_Read(void);
extern U16_T GPT_CNT_Read(void);
extern void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X);
extern void GPT_INT_ENABLE(void);
extern void GPT_INT_DISABLE(void);
extern void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
       GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx);
extern void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
      U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA);
extern void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
      GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt);
extern void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
     , GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
     GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP );
# 29 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_i2c.h" 1
# 169 "include/apt32f102_i2c.h"
typedef enum
{
    I2C_SDA_PA00= 0,
 I2C_SDA_PA03 = 1,
 I2C_SDA_PA07= 2,
    I2C_SDA_PA013= 3,
    I2C_SDA_PA014 = 4,
}I2C_SDA_TypeDef;




typedef enum
{
    I2C_SCL_PB00 = 0,
 I2C_SCL_PB02 = 1,
    I2C_SCL_PA01 = 2,
    I2C_SCL_PA04 = 3,
 I2C_SCL_PA06 = 4,
 I2C_SCL_PA015 = 5,
}I2C_SCL_TypeDef;




typedef enum
{
 STANDARD_MODE = (0x01ul << 1),
    FAST_MODE=(0x02ul << 1),
}I2C_SPEEDMODE_TypeDef;




typedef enum
{
 I2C_SLAVE_7BIT= (0x00ul << 3),
    I2C_SLAVE_10BIT=(0x01ul << 3),
}I2C_SLAVEBITS_TypeDef;




typedef enum
{
 I2C_MASTRER_7BIT= (0x00ul << 4),
    I2C_MASTRER_10BIT=(0x01ul << 4),
}I2C_MASTRERBITS_TypeDef;




extern void I2C_Master_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
        I2C_MASTRERBITS_TypeDef MASTERBITS,U16_T I2C_MASTER_ADD,U16_T SS_SCLH,U16_T SS_SCLL);
extern void I2C_Slave_CONFIG(I2C_SDA_TypeDef I2C_SDA_IO,I2C_SCL_TypeDef I2C_SCL_IO,I2C_SPEEDMODE_TypeDef SPEEDMODE,
      I2C_SLAVEBITS_TypeDef SLAVEBITS,U16_T I2C_SALVE_ADDS,U16_T SS_SCLHX,U16_T SS_SCLLX);
extern void I2C_SDA_TSETUP_THOLD_CONFIG(U8_T SDA_TSETUP , U8_T SDA_RX_THOLD , U16_T SDA_TX_THOLD);
extern void I2C_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T INT_TYPE);
extern void I2C_FIFO_TriggerData(U16_T RX_FLSEL,U16_T TX_FLSEL);
extern void I2C_Stop(void);
extern void I2C_Enable(void);
extern void I2C_Disable(void);
extern void I2C_Abort_EN(void);
extern U8_T I2C_Abort_Status(void);
extern void I2C_SDA_Recover_EN(void);
extern void I2C_SDA_Recover_DIS(void);
extern void I2C_Int_Enable(void);
extern void I2C_Int_Disable(void);
extern void I2C_WRITE_Byte(U8_T write_adds,U8_T i2c_data);
extern void I2C_WRITE_nByte(U8_T write_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern U8_T I2C_READ_Byte(U8_T read_adds);
extern void I2C_READ_nByte(U8_T read_adds,volatile U8_T *i2c_data,U8_T NumByteToWrite);
extern void I2C_Slave_Receive(void);
extern void I2C_DeInit(void);

extern volatile unsigned char I2CWrBuffer[32];
extern volatile unsigned char I2CRdBuffer[32];
extern volatile U8_T f_ERROR;
extern void I2C_SLAVE_CONFIG(void);
# 30 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_ifc.h" 1
# 68 "include/apt32f102_ifc.h"
typedef enum
{
 PROM_PageAdd0 = ((CSP_REGISTER_T)0x00000000),
 PROM_PageAdd1 = ((CSP_REGISTER_T)0x00000100),
 PROM_PageAdd2 = ((CSP_REGISTER_T)0x00000200),
 PROM_PageAdd3 = ((CSP_REGISTER_T)0x00000300),
 PROM_PageAdd4 = ((CSP_REGISTER_T)0x00000400),
 PROM_PageAdd5 = ((CSP_REGISTER_T)0x00000500),
 PROM_PageAdd6 = ((CSP_REGISTER_T)0x00000600),
 PROM_PageAdd7 = ((CSP_REGISTER_T)0x00000700),
 PROM_PageAdd8 = ((CSP_REGISTER_T)0x00000800),
 PROM_PageAdd9 = ((CSP_REGISTER_T)0x00000900),

 PROM_PageAdd10 = ((CSP_REGISTER_T)0x00000A00),
 PROM_PageAdd11 = ((CSP_REGISTER_T)0x00000B00),
 PROM_PageAdd12 = ((CSP_REGISTER_T)0x00000C00),
 PROM_PageAdd13 = ((CSP_REGISTER_T)0x00000D00),
 PROM_PageAdd14 = ((CSP_REGISTER_T)0x00000E00),
 PROM_PageAdd15 = ((CSP_REGISTER_T)0x00000F00),
 PROM_PageAdd16 = ((CSP_REGISTER_T)0x00001000),
 PROM_PageAdd17 = ((CSP_REGISTER_T)0x00001100),
 PROM_PageAdd18 = ((CSP_REGISTER_T)0x00001200),
 PROM_PageAdd19 = ((CSP_REGISTER_T)0x00001300),

 PROM_PageAdd20 = ((CSP_REGISTER_T)0x00001400),
 PROM_PageAdd21 = ((CSP_REGISTER_T)0x00001500),
 PROM_PageAdd22 = ((CSP_REGISTER_T)0x00001600),
 PROM_PageAdd23 = ((CSP_REGISTER_T)0x00001700),
 PROM_PageAdd24 = ((CSP_REGISTER_T)0x00001800),
 PROM_PageAdd25 = ((CSP_REGISTER_T)0x00001900),
 PROM_PageAdd26 = ((CSP_REGISTER_T)0x00001A00),
 PROM_PageAdd27 = ((CSP_REGISTER_T)0x00001B00),
 PROM_PageAdd28 = ((CSP_REGISTER_T)0x00001C00),
 PROM_PageAdd29 = ((CSP_REGISTER_T)0x00001D00),

 PROM_PageAdd30 = ((CSP_REGISTER_T)0x00001E00),
 PROM_PageAdd31 = ((CSP_REGISTER_T)0x00001F00),
 PROM_PageAdd32 = ((CSP_REGISTER_T)0x00002000),
 PROM_PageAdd33 = ((CSP_REGISTER_T)0x00002100),
 PROM_PageAdd34 = ((CSP_REGISTER_T)0x00002200),
 PROM_PageAdd35 = ((CSP_REGISTER_T)0x00002300),
 PROM_PageAdd36 = ((CSP_REGISTER_T)0x00002400),
 PROM_PageAdd37 = ((CSP_REGISTER_T)0x00002500),
 PROM_PageAdd38 = ((CSP_REGISTER_T)0x00002600),
 PROM_PageAdd39 = ((CSP_REGISTER_T)0x00002700),

 PROM_PageAdd40 = ((CSP_REGISTER_T)0x00002800),
 PROM_PageAdd41 = ((CSP_REGISTER_T)0x00002900),
 PROM_PageAdd42 = ((CSP_REGISTER_T)0x00002A00),
 PROM_PageAdd43 = ((CSP_REGISTER_T)0x00002B00),
 PROM_PageAdd44 = ((CSP_REGISTER_T)0x00002C00),
 PROM_PageAdd45 = ((CSP_REGISTER_T)0x00002D00),
 PROM_PageAdd46 = ((CSP_REGISTER_T)0x00002E00),
 PROM_PageAdd47 = ((CSP_REGISTER_T)0x00002F00),
 PROM_PageAdd48 = ((CSP_REGISTER_T)0x00003000),
 PROM_PageAdd49 = ((CSP_REGISTER_T)0x00003100),

 PROM_PageAdd50 = ((CSP_REGISTER_T)0x00003200),
 PROM_PageAdd51 = ((CSP_REGISTER_T)0x00003300),
 PROM_PageAdd52 = ((CSP_REGISTER_T)0x00003400),
 PROM_PageAdd53 = ((CSP_REGISTER_T)0x00003500),
 PROM_PageAdd54 = ((CSP_REGISTER_T)0x00003600),
 PROM_PageAdd55 = ((CSP_REGISTER_T)0x00003700),
 PROM_PageAdd56 = ((CSP_REGISTER_T)0x00003800),
 PROM_PageAdd57 = ((CSP_REGISTER_T)0x00003900),
 PROM_PageAdd58 = ((CSP_REGISTER_T)0x00003A00),
 PROM_PageAdd59 = ((CSP_REGISTER_T)0x00003B00),

 PROM_PageAdd60 = ((CSP_REGISTER_T)0x00003C00),
 PROM_PageAdd61 = ((CSP_REGISTER_T)0x00003D00),
 PROM_PageAdd62 = ((CSP_REGISTER_T)0x00003E00),
 PROM_PageAdd63 = ((CSP_REGISTER_T)0x00003F00),
 PROM_PageAdd64 = ((CSP_REGISTER_T)0x00004000),
 PROM_PageAdd65 = ((CSP_REGISTER_T)0x00004100),
 PROM_PageAdd66 = ((CSP_REGISTER_T)0x00004200),
 PROM_PageAdd67 = ((CSP_REGISTER_T)0x00004300),
 PROM_PageAdd68 = ((CSP_REGISTER_T)0x00004400),
 PROM_PageAdd69 = ((CSP_REGISTER_T)0x00004500),

 PROM_PageAdd70 = ((CSP_REGISTER_T)0x00004600),
 PROM_PageAdd71 = ((CSP_REGISTER_T)0x00004700),
 PROM_PageAdd72 = ((CSP_REGISTER_T)0x00004800),
 PROM_PageAdd73 = ((CSP_REGISTER_T)0x00004900),
 PROM_PageAdd74 = ((CSP_REGISTER_T)0x00004A00),
 PROM_PageAdd75 = ((CSP_REGISTER_T)0x00004B00),
 PROM_PageAdd76 = ((CSP_REGISTER_T)0x00004C00),
 PROM_PageAdd77 = ((CSP_REGISTER_T)0x00004D00),
 PROM_PageAdd78 = ((CSP_REGISTER_T)0x00004E00),
 PROM_PageAdd79 = ((CSP_REGISTER_T)0x00004F00),

 PROM_PageAdd80 = ((CSP_REGISTER_T)0x00005000),
 PROM_PageAdd81 = ((CSP_REGISTER_T)0x00005100),
 PROM_PageAdd82 = ((CSP_REGISTER_T)0x00005200),
 PROM_PageAdd83 = ((CSP_REGISTER_T)0x00005300),
 PROM_PageAdd84 = ((CSP_REGISTER_T)0x00005400),
 PROM_PageAdd85 = ((CSP_REGISTER_T)0x00005500),
 PROM_PageAdd86 = ((CSP_REGISTER_T)0x00005600),
 PROM_PageAdd87 = ((CSP_REGISTER_T)0x00005700),
 PROM_PageAdd88 = ((CSP_REGISTER_T)0x00005800),
 PROM_PageAdd89 = ((CSP_REGISTER_T)0x00005900),

 PROM_PageAdd90 = ((CSP_REGISTER_T)0x00005A00),
 PROM_PageAdd91 = ((CSP_REGISTER_T)0x00005B00),
 PROM_PageAdd92 = ((CSP_REGISTER_T)0x00005C00),
 PROM_PageAdd93 = ((CSP_REGISTER_T)0x00005D00),
 PROM_PageAdd94 = ((CSP_REGISTER_T)0x00005E00),
 PROM_PageAdd95 = ((CSP_REGISTER_T)0x00005F00),
 PROM_PageAdd96 = ((CSP_REGISTER_T)0x00006000),
 PROM_PageAdd97 = ((CSP_REGISTER_T)0x00006100),
 PROM_PageAdd98 = ((CSP_REGISTER_T)0x00006200),
 PROM_PageAdd99 = ((CSP_REGISTER_T)0x00006300),

 PROM_PageAdd100 = ((CSP_REGISTER_T)0x00006400),
 PROM_PageAdd101 = ((CSP_REGISTER_T)0x00006500),
 PROM_PageAdd102 = ((CSP_REGISTER_T)0x00006600),
 PROM_PageAdd103 = ((CSP_REGISTER_T)0x00006700),
 PROM_PageAdd104 = ((CSP_REGISTER_T)0x00006800),
 PROM_PageAdd105 = ((CSP_REGISTER_T)0x00006900),
 PROM_PageAdd106 = ((CSP_REGISTER_T)0x00006A00),
 PROM_PageAdd107 = ((CSP_REGISTER_T)0x00006B00),
 PROM_PageAdd108 = ((CSP_REGISTER_T)0x00006C00),
 PROM_PageAdd109 = ((CSP_REGISTER_T)0x00006D00),

 PROM_PageAdd110 = ((CSP_REGISTER_T)0x00006E00),
 PROM_PageAdd111 = ((CSP_REGISTER_T)0x00006F00),
 PROM_PageAdd112 = ((CSP_REGISTER_T)0x00007000),
 PROM_PageAdd113 = ((CSP_REGISTER_T)0x00007100),
 PROM_PageAdd114 = ((CSP_REGISTER_T)0x00007200),
 PROM_PageAdd115 = ((CSP_REGISTER_T)0x00007300),
 PROM_PageAdd116 = ((CSP_REGISTER_T)0x00007400),
 PROM_PageAdd117 = ((CSP_REGISTER_T)0x00007500),
 PROM_PageAdd118 = ((CSP_REGISTER_T)0x00007600),
 PROM_PageAdd119 = ((CSP_REGISTER_T)0x00007700),

 PROM_PageAdd120 = ((CSP_REGISTER_T)0x00007800),
 PROM_PageAdd121 = ((CSP_REGISTER_T)0x00007900),
 PROM_PageAdd122 = ((CSP_REGISTER_T)0x00007A00),
 PROM_PageAdd123 = ((CSP_REGISTER_T)0x00007B00),
 PROM_PageAdd124 = ((CSP_REGISTER_T)0x00007C00),
 PROM_PageAdd125 = ((CSP_REGISTER_T)0x00007D00),
 PROM_PageAdd126 = ((CSP_REGISTER_T)0x00007E00),
 PROM_PageAdd127 = ((CSP_REGISTER_T)0x00007F00),
 PROM_PageAdd128 = ((CSP_REGISTER_T)0x00008000),
 PROM_PageAdd129 = ((CSP_REGISTER_T)0x00008100),

 PROM_PageAdd130 = ((CSP_REGISTER_T)0x00008200),
 PROM_PageAdd131 = ((CSP_REGISTER_T)0x00008300),
 PROM_PageAdd132 = ((CSP_REGISTER_T)0x00008400),
 PROM_PageAdd133 = ((CSP_REGISTER_T)0x00008500),
 PROM_PageAdd134 = ((CSP_REGISTER_T)0x00008600),
 PROM_PageAdd135 = ((CSP_REGISTER_T)0x00008700),
 PROM_PageAdd136 = ((CSP_REGISTER_T)0x00008800),
 PROM_PageAdd137 = ((CSP_REGISTER_T)0x00008900),
 PROM_PageAdd138 = ((CSP_REGISTER_T)0x00008A00),
 PROM_PageAdd139 = ((CSP_REGISTER_T)0x00008B00),

 PROM_PageAdd140 = ((CSP_REGISTER_T)0x00008C00),
 PROM_PageAdd141 = ((CSP_REGISTER_T)0x00008D00),
 PROM_PageAdd142 = ((CSP_REGISTER_T)0x00008E00),
 PROM_PageAdd143 = ((CSP_REGISTER_T)0x00008F00),
 PROM_PageAdd144 = ((CSP_REGISTER_T)0x00009000),
 PROM_PageAdd145 = ((CSP_REGISTER_T)0x00009100),
 PROM_PageAdd146 = ((CSP_REGISTER_T)0x00009200),
 PROM_PageAdd147 = ((CSP_REGISTER_T)0x00009300),
 PROM_PageAdd148 = ((CSP_REGISTER_T)0x00009400),
 PROM_PageAdd149 = ((CSP_REGISTER_T)0x00009500),

 PROM_PageAdd150 = ((CSP_REGISTER_T)0x00009600),
 PROM_PageAdd151 = ((CSP_REGISTER_T)0x00009700),
 PROM_PageAdd152 = ((CSP_REGISTER_T)0x00009800),
 PROM_PageAdd153 = ((CSP_REGISTER_T)0x00009900),
 PROM_PageAdd154 = ((CSP_REGISTER_T)0x00009A00),
 PROM_PageAdd155 = ((CSP_REGISTER_T)0x00009B00),
 PROM_PageAdd156 = ((CSP_REGISTER_T)0x00009C00),
 PROM_PageAdd157 = ((CSP_REGISTER_T)0x00009D00),
 PROM_PageAdd158 = ((CSP_REGISTER_T)0x00009E00),
 PROM_PageAdd159 = ((CSP_REGISTER_T)0x00009F00),

 PROM_PageAdd160 = ((CSP_REGISTER_T)0x0000A000),
 PROM_PageAdd161 = ((CSP_REGISTER_T)0x0000A100),
 PROM_PageAdd162 = ((CSP_REGISTER_T)0x0000A200),
 PROM_PageAdd163 = ((CSP_REGISTER_T)0x0000A300),
 PROM_PageAdd164 = ((CSP_REGISTER_T)0x0000A400),
 PROM_PageAdd165 = ((CSP_REGISTER_T)0x0000A500),
 PROM_PageAdd166 = ((CSP_REGISTER_T)0x0000A600),
 PROM_PageAdd167 = ((CSP_REGISTER_T)0x0000A700),
 PROM_PageAdd168 = ((CSP_REGISTER_T)0x0000A800),
 PROM_PageAdd169 = ((CSP_REGISTER_T)0x0000A900),

 PROM_PageAdd170 = ((CSP_REGISTER_T)0x0000AA00),
 PROM_PageAdd171 = ((CSP_REGISTER_T)0x0000AB00),
 PROM_PageAdd172 = ((CSP_REGISTER_T)0x0000AC00),
 PROM_PageAdd173 = ((CSP_REGISTER_T)0x0000AD00),
 PROM_PageAdd174 = ((CSP_REGISTER_T)0x0000AE00),
 PROM_PageAdd175 = ((CSP_REGISTER_T)0x0000AF00),
 PROM_PageAdd176 = ((CSP_REGISTER_T)0x0000B000),
 PROM_PageAdd177 = ((CSP_REGISTER_T)0x0000B100),
 PROM_PageAdd178 = ((CSP_REGISTER_T)0x0000B200),
 PROM_PageAdd179 = ((CSP_REGISTER_T)0x0000B300),

 PROM_PageAdd180 = ((CSP_REGISTER_T)0x0000B400),
 PROM_PageAdd181 = ((CSP_REGISTER_T)0x0000B500),
 PROM_PageAdd182 = ((CSP_REGISTER_T)0x0000B600),
 PROM_PageAdd183 = ((CSP_REGISTER_T)0x0000B700),
 PROM_PageAdd184 = ((CSP_REGISTER_T)0x0000B800),
 PROM_PageAdd185 = ((CSP_REGISTER_T)0x0000B900),
 PROM_PageAdd186 = ((CSP_REGISTER_T)0x0000BA00),
 PROM_PageAdd187 = ((CSP_REGISTER_T)0x0000BB00),
 PROM_PageAdd188 = ((CSP_REGISTER_T)0x0000BC00),
 PROM_PageAdd189 = ((CSP_REGISTER_T)0x0000BD00),

 PROM_PageAdd190 = ((CSP_REGISTER_T)0x0000BE00),
 PROM_PageAdd191 = ((CSP_REGISTER_T)0x0000BF00),
 PROM_PageAdd192 = ((CSP_REGISTER_T)0x0000C000),
 PROM_PageAdd193 = ((CSP_REGISTER_T)0x0000C100),
 PROM_PageAdd194 = ((CSP_REGISTER_T)0x0000C200),
 PROM_PageAdd195 = ((CSP_REGISTER_T)0x0000C300),
 PROM_PageAdd196 = ((CSP_REGISTER_T)0x0000C400),
 PROM_PageAdd197 = ((CSP_REGISTER_T)0x0000C500),
 PROM_PageAdd198 = ((CSP_REGISTER_T)0x0000C600),
 PROM_PageAdd199 = ((CSP_REGISTER_T)0x0000C700),

 PROM_PageAdd200 = ((CSP_REGISTER_T)0x0000C800),
 PROM_PageAdd201 = ((CSP_REGISTER_T)0x0000C900),
 PROM_PageAdd202 = ((CSP_REGISTER_T)0x0000CA00),
 PROM_PageAdd203 = ((CSP_REGISTER_T)0x0000CB00),
 PROM_PageAdd204 = ((CSP_REGISTER_T)0x0000CC00),
 PROM_PageAdd205 = ((CSP_REGISTER_T)0x0000CD00),
 PROM_PageAdd206 = ((CSP_REGISTER_T)0x0000CE00),
 PROM_PageAdd207 = ((CSP_REGISTER_T)0x0000CF00),
 PROM_PageAdd208 = ((CSP_REGISTER_T)0x0000D000),
 PROM_PageAdd209 = ((CSP_REGISTER_T)0x0000D100),

 PROM_PageAdd210 = ((CSP_REGISTER_T)0x0000D200),
 PROM_PageAdd211 = ((CSP_REGISTER_T)0x0000D300),
 PROM_PageAdd212 = ((CSP_REGISTER_T)0x0000D400),
 PROM_PageAdd213 = ((CSP_REGISTER_T)0x0000D500),
 PROM_PageAdd214 = ((CSP_REGISTER_T)0x0000D600),
 PROM_PageAdd215 = ((CSP_REGISTER_T)0x0000D700),
 PROM_PageAdd216 = ((CSP_REGISTER_T)0x0000D800),
 PROM_PageAdd217 = ((CSP_REGISTER_T)0x0000D900),
 PROM_PageAdd218 = ((CSP_REGISTER_T)0x0000DA00),
 PROM_PageAdd219 = ((CSP_REGISTER_T)0x0000DB00),

 PROM_PageAdd220 = ((CSP_REGISTER_T)0x0000DC00),
 PROM_PageAdd221 = ((CSP_REGISTER_T)0x0000DD00),
 PROM_PageAdd222 = ((CSP_REGISTER_T)0x0000DE00),
 PROM_PageAdd223 = ((CSP_REGISTER_T)0x0000DF00),
 PROM_PageAdd224 = ((CSP_REGISTER_T)0x0000E000),
 PROM_PageAdd225 = ((CSP_REGISTER_T)0x0000E100),
 PROM_PageAdd226 = ((CSP_REGISTER_T)0x0000E200),
 PROM_PageAdd227 = ((CSP_REGISTER_T)0x0000E300),
 PROM_PageAdd228 = ((CSP_REGISTER_T)0x0000E400),
 PROM_PageAdd229 = ((CSP_REGISTER_T)0x0000E500),

 PROM_PageAdd230 = ((CSP_REGISTER_T)0x0000E600),
 PROM_PageAdd231 = ((CSP_REGISTER_T)0x0000E700),
 PROM_PageAdd232 = ((CSP_REGISTER_T)0x0000E800),
 PROM_PageAdd233 = ((CSP_REGISTER_T)0x0000E900),
 PROM_PageAdd234 = ((CSP_REGISTER_T)0x0000EA00),
 PROM_PageAdd235 = ((CSP_REGISTER_T)0x0000EB00),
 PROM_PageAdd236 = ((CSP_REGISTER_T)0x0000EC00),
 PROM_PageAdd237 = ((CSP_REGISTER_T)0x0000ED00),
 PROM_PageAdd238 = ((CSP_REGISTER_T)0x0000EE00),
 PROM_PageAdd239 = ((CSP_REGISTER_T)0x0000EF00),

 PROM_PageAdd240 = ((CSP_REGISTER_T)0x0000F000),
 PROM_PageAdd241 = ((CSP_REGISTER_T)0x0000F100),
 PROM_PageAdd242 = ((CSP_REGISTER_T)0x0000F200),
 PROM_PageAdd243 = ((CSP_REGISTER_T)0x0000F300),
 PROM_PageAdd244 = ((CSP_REGISTER_T)0x0000F400),
 PROM_PageAdd245 = ((CSP_REGISTER_T)0x0000F50),
 PROM_PageAdd246 = ((CSP_REGISTER_T)0x0000F600),
 PROM_PageAdd247 = ((CSP_REGISTER_T)0x0000F700),
 PROM_PageAdd248 = ((CSP_REGISTER_T)0x0000F800),
 PROM_PageAdd249 = ((CSP_REGISTER_T)0x0000F900),

 PROM_PageAdd250 = ((CSP_REGISTER_T)0x0000FA00),
 PROM_PageAdd251 = ((CSP_REGISTER_T)0x0000FB00),
 PROM_PageAdd252 = ((CSP_REGISTER_T)0x0000FC00),
 PROM_PageAdd253 = ((CSP_REGISTER_T)0x0000FD00),
 PROM_PageAdd254 = ((CSP_REGISTER_T)0x0000FE00),
 PROM_PageAdd255 = ((CSP_REGISTER_T)0x0000FF00),

 DROM_PageAdd0 = ((CSP_REGISTER_T)0x10000000),
 DROM_PageAdd1 = ((CSP_REGISTER_T)0x10000040),
 DROM_PageAdd2 = ((CSP_REGISTER_T)0x10000080),
 DROM_PageAdd3 = ((CSP_REGISTER_T)0x100000C0),
 DROM_PageAdd4 = ((CSP_REGISTER_T)0x10000100),
 DROM_PageAdd5 = ((CSP_REGISTER_T)0x10000140),
 DROM_PageAdd6 = ((CSP_REGISTER_T)0x10000180),
 DROM_PageAdd7 = ((CSP_REGISTER_T)0x100001C0),
 DROM_PageAdd8 = ((CSP_REGISTER_T)0x10000200),
 DROM_PageAdd9 = ((CSP_REGISTER_T)0x10000240),

 DROM_PageAdd10 = ((CSP_REGISTER_T)0x10000280),
 DROM_PageAdd11 = ((CSP_REGISTER_T)0x100002C0),
 DROM_PageAdd12 = ((CSP_REGISTER_T)0x10000300),
 DROM_PageAdd13 = ((CSP_REGISTER_T)0x10000340),
 DROM_PageAdd14 = ((CSP_REGISTER_T)0x10000380),
 DROM_PageAdd15 = ((CSP_REGISTER_T)0x100003C0),
 DROM_PageAdd16 = ((CSP_REGISTER_T)0x10000400),
 DROM_PageAdd17 = ((CSP_REGISTER_T)0x10000440),
 DROM_PageAdd18 = ((CSP_REGISTER_T)0x10000480),
 DROM_PageAdd19 = ((CSP_REGISTER_T)0x100004C0),

 DROM_PageAdd20 = ((CSP_REGISTER_T)0x10000500),
 DROM_PageAdd21 = ((CSP_REGISTER_T)0x10000540),
 DROM_PageAdd22 = ((CSP_REGISTER_T)0x10000580),
 DROM_PageAdd23 = ((CSP_REGISTER_T)0x100005C0),
 DROM_PageAdd24 = ((CSP_REGISTER_T)0x10000600),
 DROM_PageAdd25 = ((CSP_REGISTER_T)0x10000640),
 DROM_PageAdd26 = ((CSP_REGISTER_T)0x10000680),
 DROM_PageAdd27 = ((CSP_REGISTER_T)0x100006C0),
 DROM_PageAdd28 = ((CSP_REGISTER_T)0x10000700),
 DROM_PageAdd29 = ((CSP_REGISTER_T)0x10000740),

 DROM_PageAdd30 = ((CSP_REGISTER_T)0x10000780),
 DROM_PageAdd31 = ((CSP_REGISTER_T)0x100007C0)
}IFC_ROMSELETED_TypeDef;




typedef enum
{
 ERS_END_INT = (0x01ul),
 RGM_END_INT = ((0x01ul)<<1),
 PEP_END_INT = ((0x01ul)<<2),
 PROT_ERR_INT = ((0x01ul)<<12),
 UDEF_ERR_INT = ((0x01ul)<<13),
 ADDR_ERR_INT = ((0x01ul)<<14),
 OVW_ERR_INT = ((0x01ul)<<15)
}IFC_INT_TypeDef;


extern void ChipErase(void);
extern void PageErase(IFC_ROMSELETED_TypeDef XROM_PageAd);
extern void IFC_interrupt_CMD(FunctionalStatus NewState ,IFC_INT_TypeDef IFC_INT_x);
extern void IFC_Int_Enable(void);
extern void IFC_Int_Disable(void);
extern void Page_ProgramData(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void Page_ProgramData_int(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned char *BufArry);
extern void ReadDataArry(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern void ReadDataArry_U8(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned char *DataArryPoint);
extern volatile unsigned int R_INT_FlashAdd;
extern volatile unsigned char f_Drom_write_complete;
extern volatile unsigned char f_Drom_writing;
extern volatile unsigned char ifc_step;

extern void Page_ProgramData2(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned int *BufArry);
extern void Page_ProgramData3(unsigned int FlashAdd,unsigned int DataSize,volatile unsigned int Data);
extern void ReadDataArry2(unsigned int RdStartAdd,unsigned int DataLength,volatile unsigned int *DataArryPoint);
# 31 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_lpt.h" 1
# 33 "include/apt32f102_lpt.h"
typedef enum
{
    LPTCLK_DIS = 0,
 LPTCLK_EN = 1,
}LPT_CLK_TypeDef;



typedef enum
{
 LPT_PCLK_DIV4= (0<<2),
    LPT_ISCLK = (1<<2),
 LPT_IMCLK_DIV4 = (2<<2),
 LPT_EMCLK = (3<<2),
 LPT_IN_RISE = (4<<2),
 LPT_IN_FALL = (5<<2),
}LPT_CSS_TypeDef;



typedef enum
{
    LPT_SHADOW = (0<<6),
 LPT_IMMEDIATE= (1<<6),
}LPT_SHDWSTP_TypeDef;



typedef enum
{
 LPT_PSC_DIV0= 0,
 LPT_PSC_DIV2= 1,
 LPT_PSC_DIV4= 2,
    LPT_PSC_DIV8= 3,
 LPT_PSC_DIV16= 4,
 LPT_PSC_DIV32= 5,
 LPT_PSC_DIV64= 6,
 LPT_PSC_DIV128= 7,
    LPT_PSC_DIV256= 8,
 LPT_PSC_DIV512= 9,
 LPT_PSC_DIV1024= 0X0A,
 LPT_PSC_DIV2048= 0X0B,
 LPT_PSC_DIV4096= 0X0C,
}LPT_PSCDIV_TypeDef;



typedef enum
{
    LPT_SWSYNDIS= (0<<2),
 LPT_SWSYNEN= (1<<2),
}LPT_SWSYN_TypeDef;



typedef enum
{
    LPT_IDLE_Z= (0<<3),
 LPT_IDLE_LOW= (1<<3),
}LPT_IDLEST_TypeDef;



typedef enum
{
    LPT_PRDLD_IMMEDIATELY= (0<<4),
 LPT_PRDLD_DUTY_END= (1<<4),
}LPT_PRDLD_TypeDef;



typedef enum
{
    LPT_POL_HIGH= (0<<5),
 LPT_POL_LOW= (1<<5),
}LPT_POL_TypeDef;



typedef enum
{
    LPT_OPM_CONTINUOUS= (0<<6),
 LPT_OPM_ONCE= (1<<6),
}LPT_OPM_TypeDef;



typedef enum
{
    LPT_FLTIPSCLD_NULL= (0<<10),
 LPT_FLTIPSCLD_EN= (1<<10),
}LPT_FLTIPSCLD_TypeDef;



typedef enum
{
    LPT_FLTDEB_00= (0<<13),
 LPT_FLTDEB_02= (1<<13),
    LPT_FLTDEB_03= (2<<13),
 LPT_FLTDEB_04= (3<<13),
    LPT_FLTDEB_06= (4<<13),
 LPT_FLTDEB_08= (5<<13),
    LPT_FLTDEB_16= (6<<13),
 LPT_FLTDEB_32= (7<<13),
}LPT_FLTDEB_TypeDef;



typedef enum
{
    LPT_PSCLD_0= (0<<16),
 LPT_PSCLD_1= (1<<16),
}LPT_PSCLD_TypeDef;



typedef enum
{
    LPT_CMPLD_IMMEDIATELY= (0<<17),
 LPT_CMPLD_DUTY_END= (1<<17),
}LPT_CMPLD_TypeDef;



typedef enum
{
    LPT_TRGEN_DIS= (0<<0),
 LPT_TRGEN_EN= (1<<0),
}LPT_TRGENX_TypeDef;



typedef enum
{
    LPT_OSTMD_CONTINUOUS= (0<<8),
 LPT_OSTMD_ONCE= (1<<8),
}LPT_OSTMDX_TypeDef;



typedef enum
{
    LPT_AREARM_DIS= (0<<30),
 LPT_AREARM_EN= (1<<30),
}LPT_AREARM_TypeDef;



typedef enum
{
    LPT_SRCSEL_DIS= (0<<0),
 LPT_SRCSEL_EN= (1<<0),
}LPT_SRCSEL_TypeDef;



typedef enum
{
    LPT_BLKINV_DIS= (0<<4),
 LPT_BLKINV_EN= (1<<4),
}LPT_BLKINV_TypeDef;



typedef enum
{
    LPT_CROSSMD_DIS= (0<<7),
 LPT_CROSSMD_EN= (1<<7),
}LPT_CROSSMD_TypeDef;



typedef enum
{
    LPT_TRGSRC0_DIS= (0<<0),
 LPT_TRGSRC0_ZRO= (1<<0),
 LPT_TRGSRC0_PRD= (2<<0),
 LPT_TRGSRC0_ZRO_PRD= (3<<0),
 LPT_TRGSRC0_CMP= (4<<0),
}LPT_TRGSRC0_TypeDef;



typedef enum
{
    LPT_ESYN0OE_DIS= (0<<20),
 LPT_ESYN0OE_EN= (1<<20),
}LPT_ESYN0OE_TypeDef;




typedef enum
{
 LPT_TRGEV0 = (0x01 << 0),
 LPT_MATCH = (0x01 << 1),
 LPT_PEND = (0x01 << 2),
}LPT_IMSCR_TypeDef;




typedef enum
{
 LPT_OUT_PA09 = 0,
 LPT_OUT_PB01 = 1,
 LPT_IN_PA10 = 2,
}LPT_IOSET_TypeDef;





extern void LPT_DeInit(void);
extern void LPT_IO_Init(LPT_IOSET_TypeDef IONAME);
extern void LPT_Configure(LPT_CLK_TypeDef CLKX,LPT_CSS_TypeDef CSSX,LPT_SHDWSTP_TypeDef SHDWSTPX,
      LPT_PSCDIV_TypeDef PSCDIVX,U8_T FLTCKPRSX,LPT_OPM_TypeDef OPMX);
extern void LPT_Debug_Mode(FunctionalStatus NewState);
extern void LPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMP_DATA);
extern void LPT_CNT_Write(U16_T CNT_DATA);
extern U16_T LPT_PRDR_Read(void);
extern U16_T LPT_CMP_Read(void);
extern U16_T LPT_CNT_Read(void);
extern void LPT_ControlSet_Configure(LPT_SWSYN_TypeDef SWSYNX,LPT_IDLEST_TypeDef IDLESTX,LPT_PRDLD_TypeDef PRDLDX,LPT_POL_TypeDef POLX,
        LPT_FLTDEB_TypeDef FLTDEBX,LPT_PSCLD_TypeDef PSCLDX,LPT_CMPLD_TypeDef CMPLDX);
extern void LPT_SyncSet_Configure(LPT_TRGENX_TypeDef TRGENX,LPT_OSTMDX_TypeDef OSTMDX,LPT_AREARM_TypeDef AREARMX);
extern void LPT_Trigger_Configure(LPT_SRCSEL_TypeDef SRCSELX,LPT_BLKINV_TypeDef BLKINVX,LPT_CROSSMD_TypeDef CROSSMDX,LPT_TRGSRC0_TypeDef TRGSRC0X,
      LPT_ESYN0OE_TypeDef ESYN0OEX,U16_T OFFSET_DATA,U16_T WINDOW_DATA,U8_T TRGEC0PRD_DATA);
extern void LPT_Trigger_Cnt(U8_T TRGEV0CNT_DATA);
extern void LPT_Trigger_EVPS(U8_T TRGEC0PRD_DATA,U8_T TRGEV0CNT_DATA);
extern void LPT_Soft_Trigger(void);
extern void LPT_Start(void);
extern void LPT_Stop(void);
extern void LPT_Soft_Reset(void);
extern void LPT_REARM_Write(void);
extern U8_T LPT_REARM_Read(void);
extern void LPT_ConfigInterrupt_CMD(FunctionalStatus NewState,LPT_IMSCR_TypeDef LPT_IMSCR_X);
extern void LPT_INT_ENABLE(void);
extern void LPT_INT_DISABLE(void);
# 32 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_rtc.h" 1
# 49 "include/apt32f102_rtc.h"
typedef enum
{
 CLKSRC_ISOSC = (CSP_REGISTER_T)(0x00ul<<24),
 CLKSRC_IMOSC_4div = (CSP_REGISTER_T)(0x01ul<<24),
 CLKSRC_EMOSC = (CSP_REGISTER_T)(0x02ul<<24),
 CLKSRC_EMOSC_4div = (CSP_REGISTER_T)(0x03ul<<24)
}RTC_CLKSRC_TypeDef;





typedef enum
{

 ALRA_INT = ((CSP_REGISTER_T)(0x01ul << 0)),
 ALRB_INT = ((CSP_REGISTER_T)(0x01ul << 1)),
 CPRD_INT = ((CSP_REGISTER_T)(0x01ul << 2)),
 RTC_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 3)),
 RTC_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 4))
}RTC_INT_TypeDef;




 typedef enum
{
 Alarm_Second_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 7)),
 Alarm_Second_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 7)),
} RTC_Alarm_Second_mask_TypeDef;
 typedef enum
{
 Alarm_Minute_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 15)),
 Alarm_Minute_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 15)),
} RTC_Alarm_Minute_mask_TypeDef;
 typedef enum
{
 Alarm_Hour_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 23)),
 Alarm_Hour_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 23)),
} RTC_Alarm_Hour_mask_TypeDef;
 typedef enum
{
 Alarm_DataOrWeek_Compare_EN = ((CSP_REGISTER_T)(0x00ul << 31)),
 Alarm_DataOrWeek_Compare_DIS = ((CSP_REGISTER_T)(0x01ul << 31))
} RTC_Alarm_DataOrWeek_mask_TypeDef; ;



 typedef enum
{
 Alarm_data_selecte = ((CSP_REGISTER_T)(0x00ul << 30)),
 Alarm_week_selecte = ((CSP_REGISTER_T)(0x01ul << 30))
} RTC_Alarm_WeekData_select_TypeDef;



 typedef enum
{
 Alarm_A = 0,
 Alarm_B = 1
}RTC_Alarm_Register_select_TypeDef;




 typedef enum
{
 Alarm_A_pulse_output = ((CSP_REGISTER_T)(0x00ul << 10)),
 Alarm_A_High = ((CSP_REGISTER_T)(0x01ul << 10)),
 Alarm_A_Low = ((CSP_REGISTER_T)(0x02ul << 10)),
 Alarm_B_pulse_output = ((CSP_REGISTER_T)(0x04ul << 10)),
 Alarm_B_High = ((CSP_REGISTER_T)(0x05ul << 10)),
 Alarm_B_Low = ((CSP_REGISTER_T)(0x06ul << 10)),
}Rtc_Output_Mode_TypeDef;



 typedef enum
{
 COSEL_Cali_512hz = ((CSP_REGISTER_T)(0x00ul << 8)),
 COSEL_Cali_1hz = ((CSP_REGISTER_T)(0x01ul << 8)),
 COSEL_NoCali_512hz = ((CSP_REGISTER_T)(0x02ul << 8)),
 COSEL_NoCali_1hz = ((CSP_REGISTER_T)(0x03ul << 8)),
}
Rtc_ClockOutput_Mode_TypeDef;



 typedef enum
{
 Alarm_A_EN = ((CSP_REGISTER_T)(0x01ul << 3)),
 Alarm_A_DIS = ((CSP_REGISTER_T)(0x00ul << 3)),

}RTC_AlarmA_CMD_TypeDef;



 typedef enum
{
 Alarm_B_EN = ((CSP_REGISTER_T)(0x01ul << 4)),
 Alarm_B_DIS = ((CSP_REGISTER_T)(0x00ul << 4)),
}RTC_AlarmB_CMD_TypeDef;



 typedef enum
{
 RTC_24H = ((CSP_REGISTER_T)(0x00ul << 5)),
 RTC_12H = ((CSP_REGISTER_T)(0x01ul << 5)),
}RTC_FMT_MODE_TypeDef;



 typedef enum
{
 CPRD_NONE = ((CSP_REGISTER_T)(0x00ul << 13)),
 CPRD_05S = ((CSP_REGISTER_T)(0x01ul << 13)),
 CPRD_1S = ((CSP_REGISTER_T)(0x02ul << 13)),
 CPRD_1MIN = ((CSP_REGISTER_T)(0x03ul << 13)),
 CPRD_1HOUR = ((CSP_REGISTER_T)(0x04ul << 13)),
 CPRD_1DAY = ((CSP_REGISTER_T)(0x05ul << 13)),
 CPRD_1MONTH = ((CSP_REGISTER_T)(0x06ul << 13)),
}RTC_CPRD_TypeDef;



 typedef enum
{
 RTC_EVTRG_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x00ul )),
 RTC_EVTRG_TRGSRC0_AlarmA = ((CSP_REGISTER_T)(0x01ul )),
 RTC_EVTRG_TRGSRC0_AlarmB = ((CSP_REGISTER_T)(0x02ul )),
 RTC_EVTRG_TRGSRC0_AlarmAB = ((CSP_REGISTER_T)(0x03ul )),
 RTC_EVTRG_TRGSRC0_CPRD = ((CSP_REGISTER_T)(0x04ul )),
}RTC_EVTRG_TRGSRC0_TypeDef;



 typedef enum
{
 RTC_EVTRG_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x00ul<<4 )),
 RTC_EVTRG_TRGSRC1_AlarmA = ((CSP_REGISTER_T)(0x01ul<<4 )),
 RTC_EVTRG_TRGSRC1_AlarmB = ((CSP_REGISTER_T)(0x02ul<<4 )),
 RTC_EVTRG_TRGSRC1_AlarmAB = ((CSP_REGISTER_T)(0x03ul<<4 )),
 RTC_EVTRG_TRGSRC1_CPRD = ((CSP_REGISTER_T)(0x04ul<<4 )),
}RTC_EVTRG_TRGSRC1_TypeDef;
 typedef enum
{
 RTC_TRGSRC0_EN = ((CSP_REGISTER_T)(0x00ul<<20 )),
 RTC_TRGSRC0_DIS = ((CSP_REGISTER_T)(0x01ul<<20 )),
 RTC_TRGSRC1_EN = ((CSP_REGISTER_T)(0x00ul<<21 )),
 RTC_TRGSRC1_DIS = ((CSP_REGISTER_T)(0x01ul<<21 )),
}RTC_TRGSRCX_CMD_TypeDef;
typedef struct
{
 unsigned char u8Second;
    unsigned char u8Minute;
    unsigned char u8Hour;
    unsigned char u8WeekOrData;
}RTC_Alarmset_T;

typedef struct
{
    unsigned char u8Second;
    unsigned char u8Minute;
    unsigned char u8Hour;
    unsigned char u8DayOfWeek;
    unsigned char u8Day;
    unsigned char u8Month;
    unsigned char u8Year;
} RTC_time_t;





extern void RTC_RST_VALUE(void);
extern void RTCCLK_CONFIG(U16_T DIVS , U16_T DIVA , RTC_CLKSRC_TypeDef CLKSRC_X);
extern void RTC_ALM_IO_SET(Rtc_Output_Mode_TypeDef Rtc_Output_Mode_x );
extern void RTC_TIMR_DATR_SET(RTC_time_t *RTC_TimeDate);
extern void RTC_TIMR_DATR_Read(RTC_time_t *RTC_TimeDate);
extern void RTC_Alarm_TIMR_DATR_SET(RTC_Alarm_Register_select_TypeDef Alarm_x , RTC_Alarmset_T *RTC_AlarmA , RTC_Alarm_Second_mask_TypeDef RTC_Alarm_Second_x ,
      RTC_Alarm_Minute_mask_TypeDef RTC_Alarm_Minute_x , RTC_Alarm_Hour_mask_TypeDef RTC_Alarm_Hour_x,
      RTC_Alarm_DataOrWeek_mask_TypeDef RTC_Alarm_DataOrWeek_x,
      RTC_Alarm_WeekData_select_TypeDef Alarm_x_selecte);
extern void RTC_Function_Config(RTC_FMT_MODE_TypeDef RTC_FMT_MODE , RTC_CPRD_TypeDef RTC_CPRD_x , Rtc_ClockOutput_Mode_TypeDef Rtc_ClockOutput_x);
extern void RTC_TRGSRC0_Config(RTC_EVTRG_TRGSRC0_TypeDef RTC_EVTRG_TRGSRC0_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev0Prd);
extern void RTC_TRGSRC1_Config(RTC_EVTRG_TRGSRC1_TypeDef RTC_EVTRG_TRGSRC1_x , RTC_TRGSRCX_CMD_TypeDef RTC_TRGSRCX_CMD , U8_T Trgev1Prd);
extern void RTC_TRGSRC0_SWFTRG(void);
extern void RTC_TRGSRC1_SWFTRG(void);
extern void RTC_Start(void);
extern void RTC_Stop(void);
extern void RTC_AlarmA_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmA);
extern void RTC_AlarmB_TIMR_DATR_Read(RTC_Alarmset_T *RTC_AlarmB);
extern void RTC_Int_Enable(RTC_INT_TypeDef RTC_X_INT);
extern void RTC_Int_Disable(RTC_INT_TypeDef RTC_X_INT);
extern void RTC_Vector_Int_Enable(void);
extern void RTC_Vector_Int_Disable(void);
extern void RTC_WakeUp_Enable(void);
extern void RTC_WakeUp_Disable(void);
extern RTC_time_t RTC_TimeDate_buf;
extern RTC_Alarmset_T RTC_AlarmA_buf;
extern RTC_Alarmset_T RTC_AlarmB_buf;
# 33 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_sio.h" 1
# 35 "include/apt32f102_sio.h"
typedef enum
{
    SIO_PA02 = 0,
 SIO_PA03 = 1,
 SIO_PA012 = 2,
 SIO_PB01 = 3,
}SIO_IOG_TypeDef;



typedef enum
{
    SIOCLK_DIS = 0,
 SIOCLK_EN = 1,
}SIO_CLK_TypeDef;



typedef enum
{
    SIO_TXDEB_1CYCLE = (0<<1),
 SIO_TXDEB_2CYCLE = (1<<1),
 SIO_TXDEB_3CYCLE = (2<<1),
 SIO_TXDEB_4CYCLE = (3<<1),
 SIO_TXDEB_5CYCLE = (4<<1),
 SIO_TXDEB_6CYCLE = (5<<1),
 SIO_TXDEB_7CYCLE = (6<<1),
 SIO_TXDEB_8CYCLE = (7<<1),
}SIO_RXDEB_TypeDef;



typedef enum
{
    SIO_IDLE_Z = 0,
 SIO_IDLE_HIGH = 1,
 SIO_IDLE_LOW = 2,
}SIO_IDLEST_TypeDef;



typedef enum
{
    SIO_TX_LSB = (0<<2),
 SIO_TX_MSB = (1<<2),
}SIO_TXDIR_TypeDef;



typedef enum
{
    SIO_OBH_1BIT = (0<<8),
 SIO_OBH_2BIT = (1<<8),
 SIO_OBH_3BIT = (2<<8),
 SIO_OBH_4BIT = (3<<8),
 SIO_OBH_5BIT = (4<<8),
 SIO_OBH_6BIT = (5<<8),
 SIO_OBH_7BIT = (6<<8),
 SIO_OBH_8BIT = (7<<8),
}SIO_LENOBH_TypeDef;



typedef enum
{
    SIO_OBL_1BIT = (0<<11),
 SIO_OBL_2BIT = (1<<11),
 SIO_OBL_3BIT = (2<<11),
 SIO_OBL_4BIT = (3<<11),
 SIO_OBL_5BIT = (4<<11),
 SIO_OBL_6BIT = (5<<11),
 SIO_OBL_7BIT = (6<<11),
 SIO_OBL_8BIT = (7<<11),
}SIO_LENOBL_TypeDef;



typedef enum
{
    SIO_RX_RISE = 0,
 SIO_RX_FALL = 1,
 SIO_RX_RISE_FALL = 2,
}SIO_BSTSEL_TypeDef;



typedef enum
{
    SIO_RX_DEB = (0<<3),
 SIO_RX_FLT30NS = (1<<3),
}SIO_TRGMODE_TypeDef;



typedef enum
{
    SIO_RX_ALIGNDIS = (0<<28),
 SIO_RX_ALIGNEN = (1<<28),
}SIO_ALIGNEN_TypeDef;



typedef enum
{
    SIO_RX_MSB = (0<<29),
 SIO_RX_LSB = (1<<29),
}SIO_RXDIR_TypeDef;



typedef enum
{
    SIO_RMODE0 = (0<<30),
 SIO_RMODE1 = (1<<30),
}SIO_RXMODE_TypeDef;



typedef enum
{
    SIO_BREAKDIS = (0<<0),
 SIO_BREAKEN = (1<<0),
}SIO_BREAKEN_TypeDef;



typedef enum
{
    SIO_BREAKLVL_LOW = (0<<1),
 SIO_BREAKLVL_HIGH = (1<<1),
}SIO_BREAKLVL_TypeDef;



typedef enum
{
    SIO_TORSTDIS = (0<<15),
 SIO_TORSTEN = (1<<15),
}SIO_TORSTEN_TypeDef;



typedef enum
{
 SIO_TXDNE = (0x01 << 0),
 SIO_RXDNE = (0x01 << 1),
 SIO_TXBUFEMPT = (0x01 << 2),
 SIO_RXBUFEMPT = (0x01 << 3),
 SIO_BREAK = (0x01 << 4),
 SIO_TIME = (0x01 << 5),
}SIO_IMSCR_TypeDef;
# 195 "include/apt32f102_sio.h"
extern void SIO_DeInit(void);
extern void SIO_IO_Init(SIO_IOG_TypeDef IOGx);
extern void SIO_TX_Init(SIO_CLK_TypeDef CLKX,U8_T TCKPRSX);
extern void SIO_TX_Configure(SIO_IDLEST_TypeDef IDLEX,SIO_TXDIR_TypeDef TXDIRX,U8_T TXBUFLENX,U8_T TXCNTX,U8_T D0DURX,U8_T D1DURX,SIO_LENOBH_TypeDef LENOBHX,
     SIO_LENOBL_TypeDef LENOBLX,U8_T HSQX,U8_T LSQX);
extern void SIO_TXBUF_Set(U8_T D30,U8_T D28,U8_T D26,U8_T D24,U8_T D22,U8_T D20,U8_T D18,U8_T D16,
     U8_T D14,U8_T D12,U8_T D10,U8_T D08,U8_T D06,U8_T D04,U8_T D02,U8_T D00);
extern void SIO_RX_Init(SIO_CLK_TypeDef CLKX,SIO_RXDEB_TypeDef RXDEBX,U8_T DEBCKSX);
extern void SIO_RX_Configure0(SIO_BSTSEL_TypeDef BSTSELX,SIO_TRGMODE_TypeDef TRGMX,U8_T SPLCNTX,U8_T EXTRACTX,U8_T HITHRX,
     SIO_ALIGNEN_TypeDef ALIGNX,SIO_RXDIR_TypeDef RXDIRX,SIO_RXMODE_TypeDef RXMODEX,U8_T RXLENX,U8_T RXBUFLENX,U8_T RXKPRSX);
extern void SIO_RX_Configure1(SIO_BREAKEN_TypeDef BREAKX,SIO_BREAKLVL_TypeDef BREAKLVLX,U8_T BREKCNTX,SIO_TORSTEN_TypeDef TORSTX,U8_T TOCNTX);
extern void SIO_ConfigInterrupt_CMD(FunctionalStatus NewState,SIO_IMSCR_TypeDef SIO_IMSCR_X);
extern void SIO_INT_ENABLE(void);
extern void SIO_INT_DISABLE(void);
# 34 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_spi.h" 1
# 202 "include/apt32f102_spi.h"
typedef enum
{
 SPI_PORIM = ((CSP_REGISTER_T)(0x01ul << 0)),
 SPI_RTIM = ((CSP_REGISTER_T)(0x01ul << 1)),
 SPI_RXIM = ((CSP_REGISTER_T)(0x01ul << 2)),
 SPI_TXIM = ((CSP_REGISTER_T)(0x01ul << 3))
}SPI_IMSCR_TypeDef;




typedef enum
{
 SPI_G0 = 0,
    SPI_G1 = 1,
 SPI_G2 = 2
}SPI_IO_TypeDef;




typedef enum
{
 SPI_DATA_SIZE_4BIT = 3,
 SPI_DATA_SIZE_5BIT = 4,
 SPI_DATA_SIZE_6BIT = 5,
 SPI_DATA_SIZE_7BIT = 6,
 SPI_DATA_SIZE_8BIT = 7,
 SPI_DATA_SIZE_9BIT = 8,
 SPI_DATA_SIZE_10BIT = 9,
 SPI_DATA_SIZE_11BIT = 10,
 SPI_DATA_SIZE_12BIT = 11,
 SPI_DATA_SIZE_13BIT = 12,
 SPI_DATA_SIZE_14BIT = 13,
 SPI_DATA_SIZE_15BIT = 14,
 SPI_DATA_SIZE_16BIT = 15
}SPI_DATA_SIZE_TypeDef;




typedef enum
{
 SPI_SPO_0 = 0,
 SPI_SPO_1 = 1
}SPI_SPO_TypeDef;




typedef enum
{
 SPI_SPH_0 = 0,
 SPI_SPH_1 = 1
}SPI_SPH_TypeDef;




typedef enum
{
 SPI_LBM_0 = 0,
 SPI_LBM_1 = 1
}SPI_LBM_TypeDef;




typedef enum
{
 SPI_RXIFLSEL_1_8 = 0x01,
 SPI_RXIFLSEL_1_4 = 0x02,
 SPI_RXIFLSEL_1_2 = 0x04
}SPI_RXIFLSEL_TypeDef;



extern void SPI_DeInit(void);
extern void SPI_NSS_IO_Init(U8_T SPI_NSS_IO_GROUP);
extern void SPI_Master_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPO_TypeDef SPI_SPO_X , SPI_SPH_TypeDef SPI_SPH_X , SPI_LBM_TypeDef SPI_LBM_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR );
extern void SPI_Slave_Init(SPI_IO_TypeDef SPI_IO , SPI_DATA_SIZE_TypeDef SPI_DATA_SIZE_x , SPI_SPH_TypeDef SPI_SPH_X , SPI_RXIFLSEL_TypeDef SPI_RXIFLSEL_X , U8_T SPI_SCR , U8_T SPI_CPSDVSR);
extern void SPI_WRITE_BYTE(U16_T wdata);
extern void SPI_READ_BYTE(U16_T wdata , volatile U16_T *rdata , U8_T Longth);
extern void SPI_ConfigInterrupt_CMD(FunctionalStatus NewState,SPI_IMSCR_TypeDef SPI_IMSCR_X);
extern void SPI_Int_Enable(void);
extern void SPI_Int_Disable(void);
extern void SPI_Wakeup_Enable(void);
extern void SPI_Wakeup_Disable(void);
# 35 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_syscon.h" 1
# 145 "include/apt32f102_syscon.h"
typedef enum
{
 ENDIS_ISOSC = (CSP_REGISTER_T)(0x01ul),
 ENDIS_IMOSC = (CSP_REGISTER_T)(0x01ul<<1),
 ENDIS_EMOSC = (CSP_REGISTER_T)(0x01ul<<3),
 ENDIS_HFOSC = (CSP_REGISTER_T)(0x01ul<<4),
 ENDIS_IDLE_PCLK = (CSP_REGISTER_T)(0x01ul<<8),
 ENDIS_SYSTICK = (CSP_REGISTER_T)(0x01ul<<11)
}SYSCON_General_CMD_TypeDef;




typedef enum
{
 SYSCLK_IMOSC = (CSP_REGISTER_T)0x0ul,
 SYSCLK_EMOSC = (CSP_REGISTER_T)0x1ul,
 SYSCLK_HFOSC = (CSP_REGISTER_T)0x2ul,
 SYSCLK_ISOSC = (CSP_REGISTER_T)0x4ul

}SystemCLK_TypeDef;



typedef enum
{
 HCLK_DIV_1 = (CSP_REGISTER_T)(0x1ul<<8),
 HCLK_DIV_2 = (CSP_REGISTER_T)(0x2ul<<8),
 HCLK_DIV_3 = (CSP_REGISTER_T)(0x3ul<<8),
 HCLK_DIV_4 = (CSP_REGISTER_T)(0x4ul<<8),
 HCLK_DIV_5 = (CSP_REGISTER_T)(0x5ul<<8),
 HCLK_DIV_6 = (CSP_REGISTER_T)(0x6ul<<8),
 HCLK_DIV_7 = (CSP_REGISTER_T)(0x7ul<<8),
 HCLK_DIV_8 = (CSP_REGISTER_T)(0x8ul<<8),
 HCLK_DIV_12 = (CSP_REGISTER_T)(0x9ul<<8),
 HCLK_DIV_16 = (CSP_REGISTER_T)(0xAul<<8),
 HCLK_DIV_24 = (CSP_REGISTER_T)(0xBul<<8),
 HCLK_DIV_32 = (CSP_REGISTER_T)(0xCul<<8),
 HCLK_DIV_64 = (CSP_REGISTER_T)(0xDul<<8),
 HCLK_DIV_128 = (CSP_REGISTER_T)(0xEul<<8),
 HCLK_DIV_256 = (CSP_REGISTER_T)(0xFul<<8)
}SystemCLK_Div_TypeDef;




typedef enum
{
 PCLK_DIV_1 = (CSP_REGISTER_T)(0x00ul<<8),
 PCLK_DIV_2 = (CSP_REGISTER_T)(0x01ul<<8),
 PCLK_DIV_4 = (CSP_REGISTER_T)(0x02ul<<8),
 PCLK_DIV_8 = (CSP_REGISTER_T)(0x04ul<<8),
 PCLK_DIV_16 = (CSP_REGISTER_T)(0x08ul<<8)
}PCLK_Div_TypeDef;




typedef enum
{
 ENABLE_LVDEN = (CSP_REGISTER_T)0x00,
 DISABLE_LVDEN = (CSP_REGISTER_T)0x0a
}X_LVDEN_TypeDef;




typedef enum
{
 INTDET_LVL_2_1V = (CSP_REGISTER_T)(0X00ul<<8),
 INTDET_LVL_2_4V = (CSP_REGISTER_T)(0X01ul<<8),
 INTDET_LVL_2_7V = (CSP_REGISTER_T)(0X02ul<<8),
 INTDET_LVL_3_0V = (CSP_REGISTER_T)(0X03ul<<8),
 INTDET_LVL_3_3V = (CSP_REGISTER_T)(0X04ul<<8),
 INTDET_LVL_3_6V = (CSP_REGISTER_T)(0X05ul<<8),
 INTDET_LVL_3_9V = (CSP_REGISTER_T)(0X06ul<<8),
}INTDET_LVL_X_TypeDef;




typedef enum
{
 RSTDET_LVL_1_9V = (CSP_REGISTER_T)(0X00ul<<12),
 RSTDET_LVL_2_2V = (CSP_REGISTER_T)(0X01ul<<12),
    RSTDET_LVL_2_5V = (CSP_REGISTER_T)(0X02ul<<12),
 RSTDET_LVL_2_8V = (CSP_REGISTER_T)(0X03ul<<12),
 RSTDET_LVL_3_1V = (CSP_REGISTER_T)(0X04ul<<12),
 RSTDET_LVL_3_4V = (CSP_REGISTER_T)(0X05ul<<12),
 RSTDET_LVL_3_7V = (CSP_REGISTER_T)(0X06ul<<12),
 RSTDET_LVL_4_0V = (CSP_REGISTER_T)(0X07ul<<12)
}RSTDET_LVL_X_TypeDef;




typedef enum
{
 ENABLE_LVD_INT = (CSP_REGISTER_T)(0X01ul<<11),
 DISABLE_LVD_INT = (CSP_REGISTER_T)(0X00ul<<11)
}X_LVD_INT_TypeDef;




typedef enum
{
 EXI_PIN0 = (CSP_REGISTER_T)(0X01ul),
 EXI_PIN1 = (CSP_REGISTER_T)(0X01ul<<1),
 EXI_PIN2 = (CSP_REGISTER_T)(0X01ul<<2),
 EXI_PIN3 = (CSP_REGISTER_T)(0X01ul<<3),
 EXI_PIN4 = (CSP_REGISTER_T)(0X01ul<<4),
 EXI_PIN5 = (CSP_REGISTER_T)(0X01ul<<5),
 EXI_PIN6 = (CSP_REGISTER_T)(0X01ul<<6),
 EXI_PIN7 = (CSP_REGISTER_T)(0X01ul<<7),
 EXI_PIN8 = (CSP_REGISTER_T)(0X01ul<<8),
 EXI_PIN9 = (CSP_REGISTER_T)(0X01ul<<9),
 EXI_PIN10 = (CSP_REGISTER_T)(0X01ul<<10),
 EXI_PIN11 = (CSP_REGISTER_T)(0X01ul<<11),
 EXI_PIN12 = (CSP_REGISTER_T)(0X01ul<<12),
 EXI_PIN13 = (CSP_REGISTER_T)(0X01ul<<13),
 EXI_PIN14 = (CSP_REGISTER_T)(0X01ul<<14),
 EXI_PIN15 = (CSP_REGISTER_T)(0X01ul<<15),
 EXI_PIN16 = (CSP_REGISTER_T)(0X01ul<<16),
 EXI_PIN17 = (CSP_REGISTER_T)(0X01ul<<17),
 EXI_PIN18 = (CSP_REGISTER_T)(0X01ul<<18),
 EXI_PIN19 = (CSP_REGISTER_T)(0X01ul<<19),
}SYSCON_EXIPIN_TypeDef;




typedef enum
{
 _EXIRT = 0,
 _EXIFT = 1,
}EXI_tringer_mode_TypeDef;





typedef enum
{
 IWDT_TIME_125MS = (CSP_REGISTER_T)(0x00ul<<8),
 IWDT_TIME_250MS = (CSP_REGISTER_T)(0x01ul<<8),
 IWDT_TIME_500MS = (CSP_REGISTER_T)(0x02ul<<8),
 IWDT_TIME_1S = (CSP_REGISTER_T)(0x03ul<<8),
 IWDT_TIME_2S = (CSP_REGISTER_T)(0x04ul<<8),
 IWDT_TIME_3S = (CSP_REGISTER_T)(0x05ul<<8),
 IWDT_TIME_4S = (CSP_REGISTER_T)(0x06ul<<8),
 IWDT_TIME_8S = (CSP_REGISTER_T)(0x07ul<<8)
}IWDT_TIME_TypeDef;




typedef enum
{
 IWDT_INTW_DIV_1 = (0x00ul<<2),
 IWDT_INTW_DIV_2 = (0x01ul<<2),
 IWDT_INTW_DIV_3 = (0x02ul<<2),
 IWDT_INTW_DIV_4 = (0x03ul<<2),
 IWDT_INTW_DIV_5 = (0x04ul<<2),
 IWDT_INTW_DIV_6 = (0x05ul<<2),
 IWDT_INTW_DIV_7 = (0x06ul<<2)
}IWDT_TIMEDIV_TypeDef;




typedef enum
{
 IMOSC_SELECTE_5556K = (0x00ul<<0),
 IMOSC_SELECTE_4194K = (0x01ul<<0),
 IMOSC_SELECTE_2097K = (0x02ul<<0),
 IMOSC_SELECTE_131K = (0x03ul<<0)
}IMOSC_SELECTE_TypeDef;




typedef enum
{
 HFOSC_SELECTE_48M = (0x0ul<<4),
 HFOSC_SELECTE_24M = (0x1ul<<4),
 HFOSC_SELECTE_12M = (0x2ul<<4),
 HFOSC_SELECTE_6M = (0x3ul<<4)
}HFOSC_SELECTE_TypeDef;




typedef enum
{
 EM_FLSEL_5ns = (0x0ul<<26),
 EM_FLSEL_10ns = (0x1ul<<26),
 EM_FLSEL_15ns = (0x2ul<<26),
 EM_FLSEL_20ns = (0x3ul<<26)
}EM_Filter_TypeDef;



typedef enum
{
 EM_FLEN_DIS = (0x0ul<<25),
 EM_FLEN_EN = (0x1ul<<25)
}EM_Filter_CMD_TypeDef;



typedef enum
{
 EM_LFSEL_DIS = (0x0ul<<10),
 EM_LFSEL_EN = (0x1ul<<10)
}EM_LFSEL_TypeDef;



typedef enum
{
 EMOSC_24M = 0,
 EMOSC_16M = 1,
 EMOSC_12M = 2,
 EMOSC_8M = 3,
 EMOSC_4M = 4,
 EMOSC_36K = 5,
 IMOSC = 6,
 ISOSC = 7,
 HFOSC_48M = 8,
 HFOSC_24M = 9,
 HFOSC_12M = 10,
 HFOSC_6M = 11
}SystemClk_data_TypeDef;
typedef enum
{
 CLO_PA02 = 0,
 CLO_PA08 = 1,
}CLO_IO_TypeDef;

typedef enum
{
 INTDET_POL_fall = (1<<6),
 INTDET_POL_X_rise = (2<<6),
 INTDET_POL_X_riseORfall = (3<<6),
}INTDET_POL_X_TypeDef;



extern void SYSCON_RST_VALUE(void);
extern void SYSCON_General_CMD(FunctionalStatus NewState, SYSCON_General_CMD_TypeDef ENDIS_X );
extern void EMOSC_OSTR_Config(U16_T EM_CNT, U8_T EM_GM,EM_LFSEL_TypeDef EM_LFSEL_X, EM_Filter_CMD_TypeDef EM_FLEN_X, EM_Filter_TypeDef EM_FLSEL_X);
extern void SystemCLK_HCLKDIV_PCLKDIV_Config(SystemCLK_TypeDef SYSCLK_X , SystemCLK_Div_TypeDef HCLK_DIV_X , PCLK_Div_TypeDef PCLK_DIV_X , SystemClk_data_TypeDef SystemClk_data_x );
extern void SYSCON_WDT_CMD(FunctionalStatus NewState);
extern void SYSCON_IWDCNT_Reload(void);
extern void SYSCON_IWDCNT_Config(IWDT_TIME_TypeDef IWDT_TIME_X , IWDT_TIMEDIV_TypeDef IWDT_INTW_DIV_X );
extern void SYSCON_LVD_Config(X_LVDEN_TypeDef X_LVDEN , INTDET_LVL_X_TypeDef INTDET_LVL_X , RSTDET_LVL_X_TypeDef RSTDET_LVL_X , X_LVD_INT_TypeDef X_LVD_INT , INTDET_POL_X_TypeDef INTDET_POL_X);
extern void EXTI_trigger_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN , EXI_tringer_mode_TypeDef EXI_tringer_mode);
extern void EXTI_interrupt_CMD(FunctionalStatus NewState , SYSCON_EXIPIN_TypeDef EXIPIN);
extern void SYSCON_CLO_CONFIG(CLO_IO_TypeDef clo_io);
extern U32_T SYSCON_Read_CINF0(void);
extern U32_T SYSCON_Read_CINF1(void);
extern void SYSCON_INT_Priority(void);
extern void EXI0_Int_Enable(void);
extern void EXI0_Int_Disable(void);
extern void EXI1_Int_Enable(void);
extern void EXI1_Int_Disable(void);
extern void EXI2_Int_Enable(void);
extern void EXI2_Int_Disable(void);
extern void EXI3_Int_Enable(void);
extern void EXI3_Int_Disable(void);
extern void EXI4_Int_Enable(void);
extern void EXI4_Int_Disable(void);
extern void SYSCON_Int_Enable(void);
extern void SYSCON_Int_Disable(void);
extern void PCLK_goto_idle_mode(void);
extern void PCLK_goto_deepsleep_mode(void);
extern void LVD_Int_Enable(void);
extern void LVD_Int_Disable(void);
extern void IWDT_Int_Enable(void);
extern void IWDT_Int_Disable(void);
extern void EXI0_WakeUp_Enable(void);
extern void EXI0_WakeUp_Disable(void);
extern void EXI1_WakeUp_Enable(void);
extern void EXI1_WakeUp_Disable(void);
extern void EXI2_WakeUp_Enable(void);
extern void EXI2_WakeUp_Disable(void);
extern void EXI3_WakeUp_Enable(void);
extern void EXI3_WakeUp_Disable(void);
extern void EXI4_WakeUp_Enable(void);
extern void EXI4_WakeUp_Disable(void);
extern void SYSCON_WakeUp_Enable(void);
extern void SYSCON_WakeUp_Disable(void);
extern void GPIO_EXTI_interrupt(CSP_GPIO_T * GPIOX,U32_T GPIO_IECR_VALUE);
extern void SYSCON_Software_Reset(void);
extern void SYSCON_HFOSC_SELECTE(HFOSC_SELECTE_TypeDef HFOSC_SELECTE_X);
extern void SYSCON_IMOSC_SELECTE(IMOSC_SELECTE_TypeDef IMOSC_SELECTE_X);
# 36 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_uart.h" 1
# 25 "include/apt32f102_uart.h"
typedef enum
{
 UART_PAR_NONE =0<<8,
 UART_PAR_EVEN =4<<8,
 UART_PAR_ODD =5<<8,
 UART_PAR_SPACE =6<<8,
 UART_PAR_MARK =7<<8
}UART_PAR_TypeDef;



typedef enum
{
    IO_UART0 = 0,
    IO_UART1 = 1,
 IO_UART2 = 2,
}UART_NUM_TypeDef;
# 91 "include/apt32f102_uart.h"
extern volatile U16_T RxDataBuf[12];
extern volatile U16_T RxDataPtr;
extern volatile U16_T TxDataPtr;
extern volatile U8_T RxDataFlag;
extern volatile U8_T TxDataFlag;


extern void UARTInit(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTClose(CSP_UART_T *uart);
extern void UARTInitRxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTInitRxTxIntEn(CSP_UART_T *uart,U16_T baudrate_u16,UART_PAR_TypeDef PAR_DAT);
extern void UARTTxByte(CSP_UART_T *uart,U8_T txdata_u8);
extern void UARTTransmit(CSP_UART_T *uart,U8_T *sourceAddress_u16,U16_T length_u16);
extern U16_T UARTRxByte(CSP_UART_T *uart,U8_T *Rxdata_u16);
extern U8_T UART_ReturnRxByte(CSP_UART_T *uart);
extern U16_T UARTReceive(CSP_UART_T *uart,U8_T *destAddress_u16,U16_T length_u16);
extern void UART0_DeInit(void);
extern void UART1_DeInit(void);
extern void UART2_DeInit(void);
extern void UART_IO_Init(UART_NUM_TypeDef IO_UART_NUM , U8_T UART_IO_G);
extern void UART0_Int_Enable(void);
extern void UART1_Int_Enable(void);
extern void UART2_Int_Enable(void);
extern void UART0_Int_Disable(void);
extern void UART1_Int_Disable(void);
extern void UART2_Int_Disable(void);
extern void UART0_WakeUp_Enable(void);
extern void UART1_WakeUp_Enable(void);
extern void UART2_WakeUp_Enable(void);
extern void UART0_WakeUp_Disable(void);
extern void UART1_WakeUp_Disable(void);
extern void UART2_WakeUp_Disable(void);
extern void UART0_CONFIG(void);
extern void UART1_CONFIG(void);
extern void UART2_CONFIG(void);
# 37 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_wwdt.h" 1
# 34 "include/apt32f102_wwdt.h"
typedef enum
{
    PCLK_4096_DIV0 = (0<<8),
 PCLK_4096_DIV2 = (1<<8),
 PCLK_4096_DIV4 = (2<<8),
 PCLK_4096_DIV8 = (3<<8),
}WWDT_PSCDIV_TypeDef;



typedef enum
{
    WWDT_DBGDIS = (0<<10),
 WWDT_DBGEN = (1<<10),
}WWDT_DBGEN_TypeDef;




extern void WWDT_DeInit(void);
extern void WWDT_CONFIG(WWDT_PSCDIV_TypeDef PSCDIVX,U8_T WND_DATA,WWDT_DBGEN_TypeDef DBGENX);
extern void WWDT_CMD(FunctionalStatus NewState);
extern void WWDT_CNT_Load(U8_T cnt_data);
extern void WWDT_Int_Config(FunctionalStatus NewState);
# 38 "apt32f102_interrupt.c" 2
# 1 "include/apt32f102_types_local.h" 1
# 39 "apt32f102_interrupt.c" 2

volatile int R_CMPA_BUF,R_CMPB_BUF;
volatile U8_T ifc_step,f_Drom_write_complete;
volatile int R_SIOTX_count,R_SIORX_count;
volatile int R_SIORX_buf[10];

extern void delay_nms(unsigned int t);





void CORETHandler(void)
{

 CK801->CORET_CVR = 0x0;


 SysTick_IRQHandler();
}





void SYSCONIntHandler(void)
{

 if((SYSCON->MISR&(0x01ul))==(0x01ul))
 {
  SYSCON->ICR = (0x01ul);
 }
 else if((SYSCON->MISR&(0x01ul<<1))==(0x01ul<<1))
 {
  SYSCON->ICR = (0x01ul<<1);
 }
 else if((SYSCON->MISR&(0x01ul<<3))==(0x01ul<<3))
 {
  SYSCON->ICR = (0x01ul<<3);
 }
 else if((SYSCON->MISR&(0x01ul<<4))==(0x01ul<<4))
 {
  SYSCON->ICR = (0x01ul<<4);
 }
 else if((SYSCON->MISR&(0x01ul<<7))==(0x01ul<<7))
 {
  SYSCON->ICR = (0x01ul<<7);
 }
 else if((SYSCON->MISR&(0x01ul<<8))==(0x01ul<<8))
 {
  SYSCON->ICR = (0x01ul<<8);

 }
 else if((SYSCON->MISR&(0x01ul<<9))==(0x01ul<<9))
 {
  SYSCON->ICR = (0x01ul<<9);
 }
 else if((SYSCON->MISR&(0X01ul<<10))==(0X01ul<<10))
 {
  SYSCON->ICR = (0X01ul<<10);
 }
 else if((SYSCON->MISR&(0x01ul<<11))==(0x01ul<<11))
 {
  SYSCON->ICR = (0x01ul<<11);
 }
 else if((SYSCON->MISR&(0X01ul<<12))==(0X01ul<<12))
 {
  SYSCON->ICR = (0X01ul<<12);
 }
 else if((SYSCON->MISR&(0X01ul<<14))==(0X01ul<<14))
 {
  SYSCON->ICR = (0X01ul<<14);
 }
 else if((SYSCON->MISR&(0x01ul<<18))==(0x01ul<<18))
 {
  SYSCON->ICR = (0x01ul<<18);
 }
 else if((SYSCON->MISR&(0x01ul<<19))==(0x01ul<<19))
 {
  SYSCON->ICR = (0x01ul<<19);
  asm ("nop");
 }
 else if((SYSCON->MISR&(0x01ul<<20))==(0x01ul<<20))
 {
  SYSCON->ICR = (0x01ul<<20);
 }
 else if((SYSCON->MISR&(0x01ul<<21))==(0x01ul<<21))
 {
  SYSCON->ICR = (0x01ul<<21);
 }
 else if((SYSCON->MISR&(0x01ul<<22))==(0x01ul<<22))
 {
  SYSCON->ICR = (0x01ul<<22);
 }
 else if((SYSCON->MISR&(0x01ul<<29))==(0x01ul<<29))
 {
  SYSCON->ICR = (0x01ul<<29);
 }
}





void IFCIntHandler(void)
{


 if(IFC->MISR&ERS_END_INT)
 {
  IFC->ICR=ERS_END_INT;
  if((ifc_step==1)&&(f_Drom_writing==1))
  {
   (IFC->KR = ((0x5A5A5A5Aul)));
   IFC->CMR=0x01;
   IFC->FM_ADDR=R_INT_FlashAdd;
   IFC->CR=0X01;
   ifc_step=2;
  }
 }
 else if(IFC->MISR&RGM_END_INT)
 {
  IFC->ICR=RGM_END_INT;
  if((ifc_step==2)&&(f_Drom_writing==1))
  {
   f_Drom_writing=0;
   f_Drom_write_complete=1;
  }
 }
 else if(IFC->MISR&PEP_END_INT)
 {
  IFC->ICR=PEP_END_INT;
  if((ifc_step==0)&&(f_Drom_writing==1))
  {
   (IFC->KR = ((0x5A5A5A5Aul)));
   IFC->CMR=0x02;
   IFC->FM_ADDR=R_INT_FlashAdd;
   IFC->CR=0X01;
   ifc_step=1;
  }
 }
 else if(IFC->MISR&PROT_ERR_INT)
 {
  IFC->ICR=PROT_ERR_INT;
 }
 else if(IFC->MISR&UDEF_ERR_INT)
 {
  IFC->ICR=UDEF_ERR_INT;
 }
 else if(IFC->MISR&ADDR_ERR_INT)
 {
  IFC->ICR=ADDR_ERR_INT;
 }
 else if(IFC->MISR&OVW_ERR_INT)
 {
  IFC->ICR=OVW_ERR_INT;
 }
}





void ADCIntHandler(void)
{

}





void EPT0IntHandler(void)
{

 if((EPT0->MISR&EPT_TRGEV0_INT)==EPT_TRGEV0_INT)
 {
  EPT0->ICR=EPT_TRGEV0_INT;
 }
 else if((EPT0->MISR&EPT_TRGEV1_INT)==EPT_TRGEV1_INT)
 {
  EPT0->ICR=EPT_TRGEV1_INT;
 }
 else if((EPT0->MISR&EPT_TRGEV2_INT)==EPT_TRGEV2_INT)
 {
  EPT0->ICR=EPT_TRGEV2_INT;
 }
 else if((EPT0->MISR&EPT_TRGEV3_INT)==EPT_TRGEV3_INT)
 {
  EPT0->ICR=EPT_TRGEV3_INT;
 }
 else if((EPT0->MISR&EPT_CAP_LD0)==EPT_CAP_LD0)
 {
  EPT0->ICR=EPT_CAP_LD0;
  EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIRT);
  EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIFT);
  R_CMPA_BUF=EPT0->CMPA;
 }
 else if((EPT0->MISR&EPT_CAP_LD1)==EPT_CAP_LD1)
 {
  EPT0->ICR=EPT_CAP_LD1;
  EXTI_trigger_CMD(ENABLE,EXI_PIN0,_EXIRT);
  EXTI_trigger_CMD(DISABLE,EXI_PIN0,_EXIFT);
  R_CMPB_BUF=EPT0->CMPB;
 }
 else if((EPT0->MISR&EPT_CAP_LD2)==EPT_CAP_LD2)
 {
  EPT0->ICR=EPT_CAP_LD2;
 }
 else if((EPT0->MISR&EPT_CAP_LD3)==EPT_CAP_LD3)
 {
  EPT0->ICR=EPT_CAP_LD3;
 }
 else if((EPT0->MISR&EPT_CAU)==EPT_CAU)
 {
  EPT0->ICR=EPT_CAU;
 }
 else if((EPT0->MISR&EPT_CAD)==EPT_CAD)
 {
  EPT0->ICR=EPT_CAD;
 }
 else if((EPT0->MISR&EPT_CBU)==EPT_CBU)
 {
  EPT0->ICR=EPT_CBU;
 }
 else if((EPT0->MISR&EPT_CBD)==EPT_CBD)
 {
  EPT0->ICR=EPT_CBD;
 }
 else if((EPT0->MISR&EPT_CCU)==EPT_CCU)
 {
  EPT0->ICR=EPT_CCU;
 }
 else if((EPT0->MISR&EPT_CCD)==EPT_CCD)
 {
  EPT0->ICR=EPT_CCD;
 }
 else if((EPT0->MISR&EPT_CDU)==EPT_CDU)
 {
  EPT0->ICR=EPT_CDU;
 }
 else if((EPT0->MISR&EPT_CDD)==EPT_CDD)
 {
  EPT0->ICR=EPT_CDD;
 }
 else if((EPT0->MISR&EPT_PEND)==EPT_PEND)
 {
  EPT0->ICR=EPT_PEND;
 }

 if((EPT0->EMMISR&EPT_EP0_EMINT)==EPT_EP0_EMINT)
 {
  EPT0->EMICR=EPT_EP0_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP1_EMINT)==EPT_EP1_EMINT)
 {
  EPT0->EMICR=EPT_EP1_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP2_EMINT)==EPT_EP2_EMINT)
 {
  EPT0->EMICR=EPT_EP2_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP3_EMINT)==EPT_EP3_EMINT)
 {
  EPT0->EMICR=EPT_EP3_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP4_EMINT)==EPT_EP4_EMINT)
 {
  EPT0->EMICR=EPT_EP4_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP5_EMINT)==EPT_EP5_EMINT)
 {
  EPT0->EMICR=EPT_EP5_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP6_EMINT)==EPT_EP6_EMINT)
 {
  EPT0->EMICR=EPT_EP6_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EP7_EMINT)==EPT_EP7_EMINT)
 {
  EPT0->EMICR=EPT_EP7_EMINT;
 }
 else if((EPT0->EMMISR&EPT_CPU_FAULT_EMINT)==EPT_CPU_FAULT_EMINT)
 {
  EPT0->EMICR=EPT_CPU_FAULT_EMINT;
 }
 else if((EPT0->EMMISR&EPT_MEM_FAULT_EMINT)==EPT_MEM_FAULT_EMINT)
 {
  EPT0->EMICR=EPT_MEM_FAULT_EMINT;
 }
 else if((EPT0->EMMISR&EPT_EOM_FAULT_EMINT)==EPT_EOM_FAULT_EMINT)
 {
  EPT0->EMICR=EPT_EOM_FAULT_EMINT;
 }
}





void WWDTHandler(void)
{
 WWDT->ICR=0X01;
 WWDT_CNT_Load(0xFF);
 if((WWDT->MISR&0X01)==0X01)
 {
  WWDT->ICR = 0X01;
 }
}





void GPT0IntHandler(void)
{


 if((GPT0->MISR&(0X01))==(0X01))
 {
  GPT0->ICR = (0X01);
 }
 else if((GPT0->MISR&(0X01<<1))==(0X01<<1))
 {
  GPT0->ICR = (0X01<<1);
 }
 else if((GPT0->MISR&(0X01<<2))==(0X01<<2))
 {
  GPT0->ICR = (0X01);
 }
 else if((GPT0->MISR&GPT_TRGEV3)==(0X01<<3))
 {
  GPT0->ICR = (0X01<<3);
 }
 else if((GPT0->MISR&(0X01<<4))==(0X01<<4))
 {
  GPT0->ICR = (0X01<<4);
 }
 else if((GPT0->MISR&(0X01<<5))==(0X01<<5))
 {
  GPT0->ICR = (0X01<<5);
 }
 else if((GPT0->MISR&(0X01<<6))==(0X01<<6))
 {
  GPT0->ICR = (0X01<<6);
 }
 else if((GPT0->MISR&(0X01<<7))==(0X01<<7))
 {
  GPT0->ICR = (0X01<<7);
 }
 else if((GPT0->MISR&(0X01<<8))==(0X01<<8))
 {
  GPT0->ICR = (0X01<<8);
 }
 else if((GPT0->MISR&(0X01<<9))==(0X01<<9))
 {
  GPT0->ICR = (0X01<<9);
 }
 else if((GPT0->MISR&(0X01<<10))==(0X01<<10))
 {
  GPT0->ICR = (0X01<<10);
 }
 else if((GPT0->MISR&(0X01<<11))==(0X01<<11))
 {
  GPT0->ICR = (0X01<<11);
 }
 else if((GPT0->MISR&(0X01<<16))==(0X01<<16))
 {
  GPT0->ICR = (0X01<<16);
 }
}





void RTCIntHandler(void)
{

 if((RTC->MISR&ALRA_INT)==ALRA_INT)
 {
  RTC->ICR=ALRA_INT;
  RTC->KEY=0XCA53;
  RTC->CR=RTC->CR|0x01;
  RTC->TIMR=(0x10<<16)|(0x00<<8)|(0x00);
  while(RTC->CR&0x02);
  RTC->CR &= ~0x1;
 }
 else if((RTC->MISR&ALRB_INT)==ALRB_INT)
 {
  RTC->ICR=ALRB_INT;
 }
 else if((RTC->IMCR&CPRD_INT)==CPRD_INT)
 {
  RTC->ICR=CPRD_INT;
 }
 else if((RTC->IMCR&RTC_TRGEV0_INT)==RTC_TRGEV0_INT)
 {
  RTC->ICR=RTC_TRGEV0_INT;
 }
 else if((RTC->IMCR&RTC_TRGEV1_INT)==RTC_TRGEV1_INT)
 {
  RTC->ICR=RTC_TRGEV1_INT;
 }
}





void UART0IntHandler(void)
{


 if ((UART0->ISR&(0x01ul << 1))==(0x01ul << 1))
 {
  UART0->ISR=(0x01ul << 1);
  RxDataFlag = 1;
 }
 else if( (UART0->ISR&(0x01ul << 0))==(0x01ul << 0) )
    {
  UART0->ISR=(0x01ul << 0);
  TxDataFlag = 1;
 }
 else if ((UART0->ISR&(0x01ul << 3))==(0x01ul << 3))
 {
  UART0->ISR=(0x01ul << 3);
 }
 else if ((UART0->ISR&(0x01ul << 2))==(0x01ul << 2))
 {
  UART0->ISR=(0x01ul << 2);
 }
}





void UART1IntHandler(void)
{


 if ((UART1->ISR&(0x01ul << 1))==(0x01ul << 1))
 {
  UART1->ISR=(0x01ul << 1);
  RxDataFlag = 1;
 }
 else if( (UART1->ISR&(0x01ul << 0))==(0x01ul << 0) )
    {
  UART1->ISR=(0x01ul << 0);
  TxDataFlag = 1;
 }
 else if ((UART1->ISR&(0x01ul << 3))==(0x01ul << 3))
 {
  UART1->ISR=(0x01ul << 3);
 }
 else if ((UART1->ISR&(0x01ul << 2))==(0x01ul << 2))
 {
  UART1->ISR=(0x01ul << 2);
 }
}





void UART2IntHandler(void)
{


 if ((UART2->ISR&(0x01ul << 1))==(0x01ul << 1))
 {
  UART2->ISR=(0x01ul << 1);
  RxDataFlag = 1;
 }
 else if( (UART2->ISR&(0x01ul << 0))==(0x01ul << 0) )
    {
  UART2->ISR=(0x01ul << 0);
  TxDataFlag = 1;
 }
 else if ((UART2->ISR&(0x01ul << 3))==(0x01ul << 3))
 {
  UART2->ISR=(0x01ul << 3);
 }
 else if ((UART2->ISR&(0x01ul << 2))==(0x01ul << 2))
 {
  UART2->ISR=(0x01ul << 2);
 }
}





void I2CIntHandler(void)
{

 I2C_Slave_Receive();
}





void SPI0IntHandler(void)
{

 if((SPI0->MISR&SPI_PORIM)==SPI_PORIM)
 {
  SPI0->ICR = SPI_PORIM;
 }
 else if((SPI0->MISR&SPI_RTIM)==SPI_RTIM)
 {
  SPI0->ICR = SPI_RTIM;
 }
 else if((SPI0->MISR&SPI_RXIM)==SPI_RXIM)
 {
  SPI0->ICR = SPI_RXIM;
# 606 "apt32f102_interrupt.c"
 }
 else if((SPI0->MISR&SPI_TXIM)==SPI_TXIM)
 {
  SPI0->ICR = SPI_TXIM;
 }

}





void SIO0IntHandler(void)
{
# 661 "apt32f102_interrupt.c"
 if(SIO0->MISR&0X02)
 {
  SIO0->ICR=0X02;
  if(R_SIORX_count>=1)
  {
   R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF&0xff000000;
   asm ("nop");
   R_SIORX_count=0;
  }
 }
 else if(SIO0->MISR&0X08)
 {
  SIO0->ICR=0X08;
  if(R_SIORX_count<1)
  {
   R_SIORX_buf[R_SIORX_count]=SIO0->RXBUF;
   R_SIORX_count++;
  }
 }
 else if(SIO0->MISR&0X010)
 {
  SIO0->ICR=0X10;
 }
 else if(SIO0->MISR&0X020)
 {
  SIO0->ICR=0X20;
 }
}





void EXI0IntHandler(void)
{

 if ((SYSCON->EXIRS&EXI_PIN0)==EXI_PIN0)
 {
  SYSCON->EXICR = EXI_PIN0;
 }
}






void EXI1IntHandler(void)
{

 if ((SYSCON->EXIRS&EXI_PIN1)==EXI_PIN1)
 {
  SYSCON->EXICR = EXI_PIN1;
 }
}





void EXI2to3IntHandler(void)
{

 if ((SYSCON->EXIRS&EXI_PIN2)==EXI_PIN2)
 {
  SYSCON->EXICR = EXI_PIN2;
 }
 else if ((SYSCON->EXIRS&EXI_PIN3)==EXI_PIN3)
 {
  SYSCON->EXICR = EXI_PIN3;
 }
}





void EXI4to9IntHandler(void)
{

 if ((SYSCON->EXIRS&EXI_PIN4)==EXI_PIN4)
 {
  SYSCON->EXICR = EXI_PIN4;
 }
 else if ((SYSCON->EXIRS&EXI_PIN5)==EXI_PIN5)
 {
  SYSCON->EXICR = EXI_PIN5;
 }
 else if ((SYSCON->EXIRS&EXI_PIN6)==EXI_PIN6)
 {
  SYSCON->EXICR = EXI_PIN6;
 }
 else if ((SYSCON->EXIRS&EXI_PIN7)==EXI_PIN7)
 {
  SYSCON->EXICR = EXI_PIN7;
 }
 else if ((SYSCON->EXIRS&EXI_PIN8)==EXI_PIN8)
 {
  SYSCON->EXICR = EXI_PIN8;
 }
 else if ((SYSCON->EXIRS&EXI_PIN9)==EXI_PIN9)
 {
  SYSCON->EXICR = EXI_PIN9;
 }

}
# 807 "apt32f102_interrupt.c"
void CNTAIntHandler(void)
{


}





void LPTIntHandler(void)
{


 if((LPT->MISR&LPT_TRGEV0)==LPT_TRGEV0)
 {
  LPT->ICR = LPT_TRGEV0;
 }
 else if((LPT->MISR&LPT_MATCH)==LPT_MATCH)
 {
  LPT->ICR = LPT_MATCH;
 }
 else if((LPT->MISR&LPT_PEND)==LPT_PEND)
 {
  LPT->ICR = LPT_PEND;
 }
}





void BT0IntHandler(void)
{

 if((BT0->MISR&BT_PEND)==BT_PEND)
 {
  BT0->ICR = BT_PEND;
 }
 else if((BT0->MISR&BT_CMP)==BT_CMP)
 {
  BT0->ICR = BT_CMP;
 }
 else if((BT0->MISR&BT_OVF)==BT_OVF)
 {
  BT0->ICR = BT_OVF;
 }
 else if((BT0->MISR&BT_EVTRG)==BT_EVTRG)
 {
  BT0->ICR = BT_EVTRG;
 }
}





void BT1IntHandler(void)
{

 if((BT1->MISR&BT_PEND)==BT_PEND)
 {
  BT1->ICR = BT_PEND;
 }
 else if((BT0->MISR&BT_CMP)==BT_CMP)
 {
  BT1->ICR = BT_CMP;
 }
 else if((BT0->MISR&BT_OVF)==BT_OVF)
 {
  BT1->ICR = BT_OVF;
 }
 else if((BT0->MISR&BT_EVTRG)==BT_EVTRG)
 {
  BT1->ICR = BT_EVTRG;
 }
}



void PriviledgeVioHandler(void)
{


}

void SystemDesPtr(void)
{


}

void MisalignedHandler(void)
{


}

void IllegalInstrHandler(void)
{


}

void AccessErrHandler(void)
{


}

void BreakPointHandler(void)
{


}

void UnrecExecpHandler(void)
{


}

void Trap0Handler(void)
{


}

void Trap1Handler(void)
{


}

void Trap2Handler(void)
{


}

void Trap3Handler(void)
{


}

void PendTrapHandler(void)
{


}
